PIC18LF8490-I/PT Microchip Technology, PIC18LF8490-I/PT Datasheet - Page 43

• Manufacturer Part Number: PIC18LF8490-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8490-I/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 66
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI, I2C, EUSART, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.0
PIC18F6390/6490/8390/8490 devices offer a total of
seven operating modes for more efficient power
management. These modes provide a variety of
options for selective power conservation in applications
where resources may be limited (i.e., battery-powered
devices).
There are three categories of power-managed modes:
• Sleep mode
• Idle modes
• Run modes
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
The
power-saving features. One of these is the clock
switching feature, offered in other PIC18 devices,
allowing the controller to use the Timer1 oscillator in
place of the primary oscillator. Also included is the
Sleep mode, offered by all PIC
device clocks are stopped.
3.1
Selecting a power-managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit controls CPU clocking, while the
SCS1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
TABLE 3-1:
© 2007 Microchip Technology Inc.
Sleep
PRI_RUN
SEC_RUN
RC_RUN
PRI_IDLE
SEC_IDLE
RC_IDLE
Note 1:
Mode
2:
power-managed
POWER-MANAGED MODES
Selecting Power-Managed Modes
IDLEN reflects its value when the SLEEP instruction is executed.
Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
IDLEN
POWER-MANAGED MODES
OSCCON<7,1:0>
N/A
N/A
N/A
0
1
1
1
(1)
modes
SCS1:SCS0
N/A
®
00
01
1x
00
01
1x
devices, where all
include
Clocked
Clocked
Clocked
PIC18F6390/6490/8390/8490
CPU
Module Clocking
Off
Off
Off
Off
several
Peripherals
Clocked
Clocked
Clocked
Clocked
Clocked
Clocked
Off
3.1.1
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:
• the primary clock, as defined by the
• the secondary clock (the Timer1 oscillator)
• the internal oscillator block (for RC modes)
3.1.2
Entering power-managed Run mode, or switching from
one power-managed mode to another, begins by
loading the OSCCON register. The SCS1:SCS0 bits
select the clock source and determine which Run or
Idle mode is being used. Changing these bits causes
an immediate switch to the new clock source,
assuming that it is running. The switch may also be
subject to clock transition delays. These are discussed
in Section 3.1.3 “Clock Transitions and Status
Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many transi-
tions may be done by changing the oscillator select
bits, or changing the IDLEN bit prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
FOSC3:FOSC0 Configuration bits
Primary – LP, XT, HS, HSPLL, RC, EC, INTRC
This is the normal, full-power execution mode.
Secondary – Timer1 Oscillator
Internal Oscillator Block
Primary – LP, XT, HS, HSPLL, RC, EC
Secondary – Timer1 Oscillator
Internal Oscillator Block
None – All clocks are disabled
Available Clock and Oscillator Source
CLOCK SOURCES
ENTERING POWER-MANAGED
MODES
(2)
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DS39629C-page 41
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