USBN9603-28M National Semiconductor, USBN9603-28M Datasheet - Page 48

• Manufacturer Part Number: USBN9603-28M
• Description: USB Controller IC
• Manufacturer: National Semiconductor

Specifications of USBN9603-28M

• Interface: USB
• No. Of Pins: 28
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 7V
• Leaded Process Compatible: No
• Controller Type, Ic: USB
• Package / Case: 28-WSOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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7.0 Register Set
IGN_ISOMSK
Ignore ISO Mask. This bit has an effect only if the endpoint is set to be isochronous. If set, this bit disables locking of specific
frame numbers with the alternate function of the TOGGLE bit. Thus data is transmitted upon reception of the next IN token.
If reset, data is only transmitted when FNL0 matches TOGGLE. This bit is cleared on reset.
7.2.23 Transmit Data X Register (TXD1, TXD2, TXD3)
Each transmit FIFO has one Transmit Data register with the bits defined below.
TXFD
Transmit FIFO Data Byte. See “Transmit Endpoint FIFO Operation (TXFIFO1, TXFIFO2, TXFIFO3)” in Section 6.2.2 for a
description of endpoint FIFO data handling. The firmware is expected to write only the packet payload data. PID and CRC16
are inserted automatically in the transmit data stream.
7.2.24 Receive Status X Register (RXS1, RXS2, RXS3)
Each receive endpoint pipe (2, 4 and 6) has one Receive Status register with the bits defined below. To allow a SETUP
packet to be received after a zero length OUT packet is received, hardware contains two copies of this register. One holds
the receive status of a zero length packet, and another holds the status of the next SETUP packet with data. If a zero length
packet is followed by a SETUP packet, the first read of this register indicates the zero length packet status, and the second
read, the SETUP packet status.
RCOUNT
Receive Count. This bit indicates the count of bytes presently in the endpoint receive FIFO. If this count is greater than 15,
a value of 15 is reported.
RX_LAST
Receive Last. This bit indicates that an ACK was sent upon completion of a successful receive operation. This bit is cleared
when this register is read.
TOGGLE
The function of this bit differs depending on whether ISO (ISO in the EPCx register is set) or non-ISO operation (ISO is reset)
is used.
For non-ISO operation, a value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of
1 indicates that this packet had a DATA1 PID.
RX_ERR
bit 7
bit 7
CoR
0
(Continued)
bit 6
SETUP
CoR
bit 6
0
1
0
0
1
1
Table 8. Set Transmit FIFO Warning Limit
TFWL
bit 5
TOGGLE
CoR HW
bit 5
0
0
0
1
0
1
bit 4
RX_LAST
Bytes Remaining in FIFO
TXFD
48
bit 4
CoR
w
-
0
TFWL disabled
bit 3
16
bit 3
4
8
0
bit 2
bit 2
RCOUNT3-0
0
bit 1
r
bit 1
0
bit 0
bit 0
0