USBN9603-28M National Semiconductor, USBN9603-28M Datasheet - Page 50

• Manufacturer Part Number: USBN9603-28M
• Description: USB Controller IC
• Manufacturer: National Semiconductor

Specifications of USBN9603-28M

• Interface: USB
• No. Of Pins: 28
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 7V
• Leaded Process Compatible: No
• Controller Type, Ic: USB
• Package / Case: 28-WSOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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7.0 Register Set
7.2.26 Receive Data X Register (RXD1, RXD2, RXD3)
Each of the three Receive Endpoint FIFOs has one Receive Data register with the bits defined below.
RXFD
Receive FIFO Data Byte. See “Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3)” in Section 6.2.2 for a
description of Endpoint FIFO data handling.
The firmware should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state
machine.
7.3 REGISTER MAP
Table 10 lists all USBN9603 registers, their addresses and their abbreviations.
bit 7
(Continued)
Address
bit 6
0x0A
0x0B
0x0C
0x0D
0x0E
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
bit 5
Table 10. USBN9603 Memory Map
Reserved
DMACNTRL
Mnemonic
DMAMSK
MCNTRL
NAKMSK
Register
ALTMSK
FWMSK
MAMSK
CCONF
RXMSK
DMAEV
TXMSK
NAKEV
ALTEV
MAEV
FWEV
NFSR
RXEV
TXEV
FNH
FAR
FNL
MIR
RID
bit 4
RXFD
50
-
r
Main Control
Clock Configuration
Revision Identifier
Function Address
Node Functional State
Main Event
Main Mask
Alternate Event
Alternate Mask
Transmit Event
Transmit Mask
Receive Event
Receive Mask
NAK Event
NAK Mask
FIFO Warning Event
FIFO Warning Mask
Frame Number High Byte
Frame Number Low Byte
DMA Control
DMA Event
DMA Mask
Mirror
bit 3
Register Name
bit 2
bit 1
bit 0