WS02-CXPC1-EV2.0 Omron, WS02-CXPC1-EV2.0 Datasheet - Page 23

• Manufacturer Part Number: WS02-CXPC1-EV2.0
• Description: Development Software
• Manufacturer: Omron

Specifications of WS02-CXPC1-EV2.0

• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: WS02CXPC1EV20

J LOGIC INSTRUCTIONS
J SHIFT INSTRUCTIONS
J SPECIAL CALCULATION INSTRUCTION
J SUBROUTINE INSTRUCTIONS
J INTERRUPT CONTROL INSTRUCTIONS
SRM1
Instruction
COMPLEMENT
LOGICAL AND
LOGICAL OR
EXCLUSIVE OR
EXCLUSIVE NOR
Instruction
SHIFT REGISTER
WORD SHIFT
ASYNCHRONOUS SHIFT REGISTER
ARITHMETIC SHIFT LEFT
ARITHMETIC SHIFT RIGHT
ROTATE LEFT
ROTATE RIGHT
ONE DIGIT SHIFT LEFT
ONE DIGIT SHIFT RIGHT
REVERSIBLE SHIFT REGISTER
Instruction
BIT COUNTER
Instruction
SUBROUTINE ENTER
SUBROUTINE ENTRY
SUBROUTINE RETURN
MACRO
Instruction
INTERVAL TIMER
INTERRUPT CONTROL
Mnemonic
COM(@)
ANDW(@)
ORW(@)
XORW(@)
XNRW(@)
Mnemonic
SFT
WSFT(@)
ASFT(@)†
ASL(@)
ASR(@)
ROL(@)
ROR(@)
SLD(@)
SRD(@)
SFTR(@)
Mnemonic
BCNT(@)†
Mnemonic
SBS(@)
SBN
RET
MCRO
Mnemonic
STIM(@)†
INT(@)†
Code
29
34
35
36
37
Code
f/10
16
17
25
26
27
28
74
75
84
Code
67
Code
91
92
93
99
Code
69
89
J PERIPHERAL DEVICE CONTROL
I/O Unit Instructions
Display Instruction
High-speed Counter Control Instructions
J DAMAGE DIAGNOSIS INSTRUCTIONS
J SPECIAL SYSTEM INSTRUCTIONS
J RS-232C INSTRUCTIONS
J DATA CONTROL INSTRUCTIONS
Note: f:
Instruction
7-SEGMENT DECODER
I/O REFRESH
Instruction
MESSAGE
Instruction
MODE CONTROL
PV READ
COMPARE TABLE LOAD
Instruction
FAILURE ALARM
SEVERE FAILURE ALARM
Instruction
SET CARRY
CLEAR CARRY
Instruction
RECEIVE
TRANSMIT
FCS CALCULATE
ASCII-TO-HEXADECIMAL
CHANGE RS-232C SETUP
Instruction
SCALE (-V2 models only)
PID CONTROL (-V2 models only)
(@): Instruction can be differentiated using input rise time
––:
†:
Instruction keys allocated to the Programming
Console.
to execute the instruction in just one cycle.
Identifies an expansion instruction.
Identifies an expansion instruction assigned a
default code.
Mnemonic
SDEC(@)
IORF(@)
Mnemonic
MSG(@)
Mnemonic
INI(@)†
PRV(@)†
CTBL(@)†
Mnemonic
FAL(@)
FALS
Mnemonic
STC(@)
CLC(@)
Mnemonic
RXD(@)†
TXD(@)†
FCS(@)
HEX(@)
STUP(@)
Mnemonic
SCL(@)†
PID
SRM1
Code
78
97
Code
46
Code
61
62
63
Code
06
07
Code
40
41
Code
47
48
––
––
––
Code
66
––
23