AD9887AKSZ-140 Analog Devices Inc, AD9887AKSZ-140 Datasheet - Page 18

• Manufacturer Part Number: AD9887AKSZ-140
• Description: IC,TV/VIDEO CIRCUIT,Video Digitizer,CMOS,QFP,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9887AKSZ-140

• Applications: Graphic Cards, VGA Interfaces
• Interface: Analog and Digital
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9887A
The key to clamping is to identify a time when the graphics
system is known to be producing a black signal. Originating
from CRT displays, the electron beam is blanked by sending
a black level during horizontal retrace to prevent disturbing the
image. Most graphics systems maintain this format of sending a
black level between active video lines.
An offset is then introduced that results in the ADCs producing a
black output (Code 0x00) when the known black input is present.
The offset remains in place when other signal levels are processed,
and the entire signal is shifted to eliminate offset errors.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of Hsync. Fortunately, there is virtually always
a period following Hsync, called the back porch, when a good
black reference is provided. This is the time when clamping
should be done.
The clamp timing can be established by using the CLAMP pin
at the appropriate time (with EXTCLMP = 1). The polarity of
this signal is set by the clamp polarity bit.
An easier method of clamp timing uses the AD9887A internal
clamp timing generator. The clamp placement register is
programmed with the number of pixel clocks that should pass
after the trailing edge of Hsync before clamping starts. A second
register (clamp duration) sets the duration of the clamp. These
are both 8-bit values, providing considerable flexibility in clamp
generation. The clamp timing is referenced to the trailing edge
of Hsync, and the back porch (black reference) always follows
Hsync. To establish clamping, set the clamp placement to 0x08
(to provide eight pixel periods for the graphics signal to
stabilize after sync) and set the clamp duration to 0x14 (to allow
the clamp 20 pixel periods to re-establish the black reference).
The value of the external input coupling capacitor affects the
performance of the clamp. If the value is too small, there is an
amplitude change during a horizontal line time (between
clamping intervals). If the capacitor is too large, it takes an
excessively long time for the clamp to recover from a large
change in incoming signal offset. The recommended value
(47 nF) results in recovery from a step error of 100 mV to
within ½ LSB in 10 lines, using a clamp duration of 20 pixel
periods on a 60 Hz SXGA signal.
YUV Clamping
YUV signals are slightly different from RGB signals in that the
dc-reference level (black level in RGB signals) is at the midpoint
of the U and V video signals. For these signals, it may be necessary
to clamp to the midscale range of the ADC range (0x80), rather
than to the bottom of the ADC range (0x00).
Clamping to midscale, rather than to ground, can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that it can be
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clamped to either midscale or ground independently. These bits
(Bit 0 to Bit 2) are located in Register 0x0F.
The midscale reference voltage that each ADC clamps to is
independently provided on the R
pins. Each converter must have its own midscale reference,
because both offset adjustment and gain adjustment for each
converter affect the dc level of midscale.
During clamping, the Y and V converters are clamped to their
respective midscale reference inputs. These inputs are Pin B
and Pin R
typical connections for both RGB and YUV clamping are shown
in Figure 4. Note that even if midscale clamping is not required,
all midscale voltage outputs should be connected to ground
through a 0.1 μF capacitor.
GAIN AND OFFSET CONTROL
A block diagram of the gain and offset control integrated with
each ADC is shown in Figure 5.
The AD9887A can accommodate input signals of 0.5 V to 1.0 V
full scale. The full-scale range is set in three 8-bit registers (red
gain, green gain, and blue gain).
Code 0 gives the minimum input range (a maximum of 0.5 V);
Code 255 corresponds to the maximum input range (a minimum
of 1.0 V). Increasing the gain setting results in an image with
less contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (red offset,
green offset, and blue offset) provide independent settings for
each channel.
The offset controls provide a ±63 LSB adjustment range. This
range is connected with the full-scale range; therefore, if the
input range is doubled (from 0.5 V to 1.0 V), the offset step size
is also doubled (from 2 mV per step to 4 mV per step).
Figure 6 and Figure 7 illustrate the interaction of gain and offset
controls. The magnitude of an LSB in offset adjustment is propor-
tional to the full-scale range, which is controlled by the gain
setting. Therefore, changing the full-scale range changes the
offset (see Figure 6). The change is minimal if the offset setting
is near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same
amount as the zero-scale level.
Figure 4. Typical Clamp Configuration for RGB and YUV Applications
CLAMP
V for the U and V converters, respectively. The
0.1μF
0.1μF
0.1μF
R
R
G
G
B
B
MIDSC
MIDSC
CLAMP
MIDSC
CLAMP
MIDSC
CLAMP
V, G
V
V
V
V
V
V
MIDSC
V, and B
MIDSC
CLAMP
V
V