AD9887AKSZ-140 Analog Devices Inc, AD9887AKSZ-140 Datasheet - Page 37

• Manufacturer Part Number: AD9887AKSZ-140
• Description: IC,TV/VIDEO CIRCUIT,Video Digitizer,CMOS,QFP,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9887AKSZ-140

• Applications: Graphic Cards, VGA Interfaces
• Interface: Analog and Digital
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x0C 7:1
0x0D 7:1
Mode Control 1
0x0E 7
Table 12. Channel Mode Settings
DEMUX
0
1
0x0E 6
Table 13. Output Mode Settings
PARALLEL
0
1
A 7-bit offset binary word that sets the dc offset of the
green channel. See REDOFST (0B).
A 7-bit offset binary word that sets the dc offset of the
blue channel. See REDOFST (0B).
A bit that determines whether all pixels are presented to
a single port (Port A), or if alternating pixels are demulti-
plexed to Port A and Port B.
A bit that determines whether all pixels are
simultaneously presented to Port A and Port B upon
every second DATACK rising edge or alternately
presented to Port A and Port B upon successive
DATACK rising edges.
When DEMUX = 0, Port B outputs are in a high imped-
ance state. The maximum data rate for single-port mode
is 100 MHz. The timing diagrams show the effects of
this option.
The power-up default value is 1.
When in single-port mode (DEMUX = 0), this bit is
ignored. The timing diagrams (Figure 18 through Figure 27
and Figure 37 through Figure 39) show the effects of this
option.
The power-up default value is PARALLEL = 1.
Function
All data goes to Port A
Alternate pixels go to Port A and Port B
Function
Data is interleaved
Data is simultaneous upon every other data clock
Green Channel Offset Adjust (GREENOFST)
Blue Channel Offset Adjust (BLUEOFST)
Channel Mode
Output Mode
Rev. B | Page 37 of 52
0x0E 5
Table 14. Output Port Phase (OUTPHASE) Settings
OUTPHASE
1
0
0x0E 4
Table 15. HSYNC Output Polarity Settings
Setting
0
1
0x0E 3
Table 16. VSYNC Output Polarity Settings
Setting
0
1
One bit that determines whether even or odd pixels go to
Port A.
One bit that determines the polarity of the HSYNC
output and the SOG output. Table 15 shows the effect of
this option. SYNC indicates the logic state of the sync
pulse.
One bit that inverts the polarity of the VSYNC output.
Table 16 shows the effect of this option.
In normal operation (OUTPHASE = 0) when operating
in dual-port output mode (DEMUX = 1), the first sample
after the Hsync leading edge is presented to Port A,
every subsequent odd sample goes to Port A, and all
even samples go to Port B.
When OUTPHASE = 1, these ports are reversed and the
first sample goes to Port B.
When DEMUX = 0, this bit is ignored because data
always comes out of only Port A.
The default setting for this register is 1. This option
works on both the analog and digital interfaces.
The default setting for this register is 1. This option
works on both the analog and digital interfaces.
Output Port Phase
HSYNC Output Polarity
VSYNC Output Invert
HSYNC
Logic 1 (negative polarity)
Logic 0 (positive polarity)
First Pixel After Hsync
Port B
Port A
VSYNC Output
Invert
No invert
AD9887A