AD9887AKSZ-140 Analog Devices Inc, AD9887AKSZ-140 Datasheet - Page 48

• Manufacturer Part Number: AD9887AKSZ-140
• Description: IC,TV/VIDEO CIRCUIT,Video Digitizer,CMOS,QFP,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9887AKSZ-140

• Applications: Graphic Cards, VGA Interfaces
• Interface: Analog and Digital
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9887A
THEORY OF OPERATION—SYNC PROCESSING
SYNC STRIPPER
The purpose of the sync stripper is to extract the sync signal
from the green graphics channel. A sync signal is not present on
all graphics systems, only those with sync-on-green. The sync
signal is extracted from the green channel in a two-step process.
First, the SOG input is clamped to its negative peak (typically
0.3 V below the black level). Next, the signal goes to a comparator
with a trigger level that is 0.15 V above the clamped level. The
output signal is typically a composite sync signal containing
both Hsync and Vsync.
SYNC SEPARATOR
A sync separator extracts the Vsync signal from a composite
sync signal by using a low-pass filter-like or integrator-like
operation. It works on the idea that the Vsync signal stays active
much longer than the Hsync signal. Therefore, it rejects any signal
shorter than a threshold value, which is somewhere in the range
between an Hsync pulse width and a Vsync pulse width.
The sync separator on the AD9887A is simply an 8-bit digital
counter with a 5 MHz clock. It works independently of the
polarity of the composite sync signal. (Polarities are determined
elsewhere on the chip.)
HSYNC IN
VSYNC IN
COAST
SOG
ACTIVITY
DETECT
ACTIVITY
SYNC STRIPPER
DETECT
NEGATIVE PEAK
POLARITY
DETECT
CLAMP
Figure 43. Sync Processing Block Diagram
PLL
COMP
SYNC
ACTIVITY
DETECT
MUX 2
MUX 3
MUX 4
Rev. B | Page 48 of 52
HSYNC
COAST
POLARITY
POLARITY
DETECT
DETECT
MUX 1
The basic idea is that the counter counts up when Hsync pulses
are present. Since Hsync pulses are relatively short in width, the
counter only reaches a value of N before the pulse ends. It then
starts counting down, eventually reaching 0 before the next
Hsync pulse arrives. The specific value of N varies among video
modes, but is always less than 255. For example, with a 1 μs
width Hsync, the counter only reaches 5 (1 μs/200 ns = 5).
When Vsync is present on the composite sync, the counter also
counts up. Because the Vsync signal is much longer, it counts to
a higher number M. For most video modes, M is at least 255.
Therefore, Vsync can be detected on the composite sync signal
by detecting when the counter counts to higher than N. The
specific count that triggers detection, the threshold count (T),
can be programmed through the serial Register 0x0F. Once
Vsync is detected, there is a similar process to detect when it
becomes inactive. Upon detection, the counter first resets to 0,
then counts up when Vsync disappears. Similar to the previous
case, it detects the absence of Vsync when the counter reaches
T. In this way, it rejects noise and/or serration pulses. Once
Vsync is detected to be absent, the counter resets to 0 and
begins the cycle again.
GENERATOR
CLOCK
SYNC SEPARATOR
INTEGRATOR
1/S
HSYNC OUT
PIXEL CLOCK
AD9887A
POLARITY
INVERT
VSYNC
SOG OUT
HSYNC OUT
VSYNC OUT