AD9887AKSZ-140 Analog Devices Inc, AD9887AKSZ-140 Datasheet - Page 38

• Manufacturer Part Number: AD9887AKSZ-140
• Description: IC,TV/VIDEO CIRCUIT,Video Digitizer,CMOS,QFP,160PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9887AKSZ-140

• Applications: Graphic Cards, VGA Interfaces
• Interface: Analog and Digital
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9887A
0x0F 7
Table 17. HSYNC Input Polarity (HSPOL) Settings
HSPOL
0
1
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Table 18. COAST Input Polarity (CSTPOL) Settings
CSTPOL
0
1
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Table 19. Clamp Input Signal Source (EXTCLMP) Settings
EXTCLMP
0
1
A bit that must be set to indicate the polarity of the
Hsync signal that is applied to the PLL HSYNC input.
Active low is the traditional negative-going Hsync pulse.
All timing is based on the leading edge of Hsync, which
is the falling edge. The rising edge has no effect.
Active high is inverted from the traditional Hsync, with
a positive-going pulse; therefore, timing is based on the
leading edge of Hsync, which is now the rising edge.
The device operates if this bit is set incorrectly, but the
internally generated clamp position, as established by
CLPOS, will not be placed as expected, which might
generate clamping errors.
The power-up default value is HSPOL = 1.
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
Active low means that the clock generator ignores HSYNC
inputs when coast is low and continues operating at the
same nominal frequency until coast goes high.
Active high means that the clock generator ignores HSYNC
inputs when coast is high and continues operating at the
same nominal frequency until coast goes low.
This function must be used with the COAST polarity
override bit (Register 0x14, Bit 1).
The power-up default value is CSTPOL = 1.
A bit that determines the source of clamp timing.
Logic 0 enables the clamp timing circuitry controlled by
CLPLACE and CLDUR. The clamp position and
duration is counted from the trailing edge of Hsync.
HSYNC Input Polarity
COAST Input Polarity
Clamp Input Signal Source
Function
Internally generated clamp
Externally provided clamp signal
Function
Active low
Active high
Function
Active low
Active high
Rev. B | Page 38 of 52
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Table 20. CLAMP Input Signal Polarity (EXTCLMP) Settings
EXTCLMP
0
1
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Table 21. External Clock Select (EXTCLK) Settings
EXTCLK
0
1
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Table 22. Red Clamp Select Settings
Clamp
0
1
Logic 1 enables the external CLAMP input pin. The
three channels are clamped when the CLAMP signal is
active. The polarity of CLAMP is determined by the
CLAMPOL bit.
The power-up default value is EXTCLMP = 0.
A bit that determines the polarity of the externally
provided CLAMP signal.
Logic 0 means that the circuit clamps when CLAMP is high
and passes the signal to the ADC when CLAMP is low.
Logic 1 means that the circuit clamps when CLAMP is low
and passes the signal to the ADC when CLAMP is high.
The power-up default value is CLAMPOL = 1.
A bit that determines the source of the pixel clock.
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided Hsync.
A Logic 1 enables the external CKEXT input pin. In this
mode, the PLL divide ratio (PLLDIV) is ignored and the
clock phase adjust (PHASE) is still functional.
The power-up default value is EXTCLK = 0.
A bit that determines whether the red channel is
clamped to ground or to midscale. For RGB video, all
three channels are referenced to ground. For YCbCr (or
YUV), the Y channel is referenced to ground, but the
CbCr channels are referenced to midscale. Clamping to
midscale actually clamps to Pin 118, R
The default setting for this register is 0.
CLAMP Input Signal Polarity
External Clock Select
Red Clamp Select
Clamp to ground
Function
Clamp to midscale (Pin 118)
Function
Internally generated clock
Externally provided clock signal
Function
Active low
Active high
CLAMP
V.