ADAU1445YSVZ-3A-RL Analog Devices Inc, ADAU1445YSVZ-3A-RL Datasheet - Page 45

• Manufacturer Part Number: ADAU1445YSVZ-3A-RL
• Description: 175MHZ SigmaDSP,2x8 SRCs
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r
• Type: Audio Processorr

Specifications of ADAU1445YSVZ-3A-RL

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Format: Fixed Point
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Routing Matrix Functionality
Serial Input Ports
The far left side of Figure 36 represents the audio input pins to
the ADAU1445/ADAU1446, namely SDATA_IN0 to SDATA_IN8
and SPDIFI. The serial audio data signals can be represented in
any standard mode, including time division multiplexing (TDM)
modes, as detailed in the Serial Data Input/Output section. After
passing through the serial input ports, the signals undergo an
automatic input channel assignment procedure.
Automatic Input Channel Assignment
The serial input ports can handle up to nine input signals. A
standard data format is I
both the left and right channels of a stereo pair. However, some
of the signals input to the serial input ports may contain data, in
TDM format, for more than two channels. The input to the
FARM allows for 24 channels, or 12 stereo pairs. Therefore, a
method is required to decompose nine signals (containing two
or more channels) into 12 stereo audio channel pairs. This is
accomplished by the automatic input channel assignment block.
In sequential order, each input signal is appropriated a number
of input channels corresponding to its channel content.
In the example shown in Figure 37, there are four input signals
to the serial input ports: SDATA_IN0 (I
SDATA_IN2 (TDM4), and SDATA_IN3 (I
containing two channels (I
Input Channel 1. SDATA_IN1, containing eight channels (TDM8),
SDATA_IN1 (TDM8)
SDATA_IN2 (TDM4)
SDATA_IN0 (I
SDATA_IN3 (I
Figure 37. Automatic Input Channel Assignment Example
2
2
S)
S)
SERIAL
MODES
SERIAL
PORTS
INPUT
INPUT
(×9)
2
S (inter-IC sound), which contains
2
S), is routed to Input Channel 0 and
CHANNELS
(24 CH)
INPUT
2
S), SDATA_IN1 (TDM8),
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
0, 1
2, 3
4, 5
6, 7
8, 9
2
S). SDATA_IN0,
SDATA_IN0 (I
SDATA_IN1 (TDM8)
SDATA_IN1 (TDM8)
SDATA_IN1 (TDM8)
SDATA_IN1 (TDM8)
SDATA_IN2 (TDM4)
SDATA_IN2 (TDM4)
SDATA_IN3 (I
2
2
S)
S)
Rev. A | Page 45 of 92
is routed sequentially to the 2, 3, 4, 5, 6, 7, 8, and 9 input channels.
SDATA_IN2, containing two stereo pairs (TDM4), is routed
sequentially to the 10, 11, 12, and 13 input channels. Finally,
SDATA_IN3, containing two channels (I
Channel 14 and Input Channel 15.
In this way, the input channels are filled automatically according to
the inputs and modes seen on the serial input ports.
When a pin is skipped, it is assigned to input channels regardless,
so care must be taken to select the proper input channels within
the DSP. Automatic channel assignment is entirely based on the
mode settings for a particular serial port; therefore, a port set to
a 2-channel mode is assigned to two sequential input channels,
and a port set to a 4-channel mode is assigned to four sequential
input channels, and so on. Figure 38 shows an example in which
several pins are disconnected in hardware and the corresponding
empty input channels are automatically assigned.
Figure 38. Automatic Input Channel Assignment Example with Skipped Pins
SDATA_IN1 (TDM8)
NOTES
1. THE BLACK DASHED LINES REPRESENT DISCONNECTED PINS;
INPUT CHANNELS ARE ASSIGNED AUTOMATICALLY.
SDATA_IN3 (I
(NO DATA) (I
(NO DATA) (I
2
2
2
S)
S)
S)
SERIAL
MODES
SERIAL
PORTS
INPUT
INPUT
(×9)
ADAU1445/ADAU1446
CHANNELS
(24 CH)
INPUT
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
0, 1
2, 3
4, 5
6, 7
8, 9
2
S), is routed to Input
(NO DATA)
SDATA_IN1 (TDM8)
SDATA_IN1 (TDM8)
SDATA_IN1 (TDM8)
SDATA_IN1 (TDM8)
(NO DATA)
SDATA_IN3 (I
2
S)