ADN2811ACPZ-CML Analog Devices Inc, ADN2811ACPZ-CML Datasheet
ADN2811ACPZ-CML
Specifications of ADN2811ACPZ-CML
Related parts for ADN2811ACPZ-CML
ADN2811ACPZ-CML Summary of contents
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FEATURES Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range Single reference clock frequency ...
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ADN2811 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics .............................................................. 5 ESD Caution.................................................................................. 5 Pin Configuration and Functional Descriptions.......................... 6 Definition of Terms .......................................................................... 8 Maximum, Minimum, and Typical Specifications ................... 8 Input Sensitivity and Input Overdrive....................................... ...
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SPECIFICATIONS Table VCC = V A MIN MAX, MIN Parameter QUANTIZER—DC CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Input Common-Mode Level Differential Input Sensitivity Input Overdrive Input Offset Input rms Noise QUANTIZER—AC CHARACTERISTICS Upper ...
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ADN2811 Parameter Setup Time Hold Time REFCLK DC INPUT CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Common-Mode Level TEST DATA DC INPUT CHARACTERISTICS Peak-to-Peak Differential Input Voltage LVTTL DC INPUT CHARACTERISTICS Input High Voltage Input Low Voltage Input Current LVTTL ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Lead Temperature (Soldering 10 Sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent ...
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ADN2811 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS Table 3. Pin Function Descriptions Pin No. Mnemonic Type 1 THRADJ AI 2, 26, 28, Pad VCC 16, 19, 22, 27, VEE P 29, 33, 34, 42, 43 VREF ...
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CLKOUTP T S DATAOUTP/N Figure 3. Output Timing 18 THRADJ RESISTOR VS. LOS TRIP POINT Figure 4. LOS Comparator Trip Point Programming OUTP V CML OUTN OUTP–OUTN ...
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ADN2811 DEFINITION OF TERMS MAXIMUM, MINIMUM, AND TYPICAL SPECIFICATIONS Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for ...
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LOS RESPONSE TIME The LOS response time is the delay between the removal of the input signal and the indication of loss of signal (LOS) at SDOUT. The LOS response time of the ADN2811 is 300 ns typ when the ...
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ADN2811 THEORY OF OPERATION The ADN2811 is a delay-locked and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that ...
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The gain of the loop integrator is small for high jitter frequencies, so larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. Large phase errors at high jitter ...
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ADN2811 FUNCTIONAL DESCRIPTION CLOCK AND DATA RECOVERY The ADN2811 recovers clock and data from serial bit streams at OC-48 as well as the 15/14 FEC rates. The data rate is selected by the RATE input (see Table 4). Table 4. ...
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The ADN2811 can accept any of the following reference clock frequencies: 19.44 MHz, 38.88 MHz, 77.76 MHz at LVTTL/ LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/ LVDS levels via the REFCLKN/P inputs, independent of data rate. The input buffer accepts ...
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ADN2811 ADN2811 PIN NIN 50Ω VREF SQUELCH MODE When the squelch input is driven to a TTL high state, both the clock and data outputs are set to the zero state to suppress downstream processing. If desired, this pin can ...
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APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. Power Supply Connections and Ground Planes Use of one low impedance ground plane to both analog and digital grounds is recommended. The VEE pins ...
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ADN2811 VCC 10µF VCC 0.1µF 50Ω TIA C 50Ω IN VCC µC 19.44MHz VCC VCC 100Ω 100Ω 100Ω 100Ω 0.1µ F 0.1µ F ADN2811 Figure 20. AC-Coupled Output Configuration 4 × 100Ω µC 0.1µF 1nF ...
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CHOOSING AC-COUPLING CAPACITORS The choice of ac-coupling capacitors at the input (PIN, NIN) and output (DATAOUTP, DATAOUTN) of the ADN2811 must be chosen carefully. When choosing the capacitors, the time constant formed with the two 50 Ω resistors in the ...
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ADN2811 DC-COUPLED APPLICATION The inputs to the ADN2811 can also be dc-coupled. This may be necessary in burst mode applications where there are long periods of CIDs and baseline wander cannot be tolerated. If the inputs to the ADN2811 are ...
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OUTLINE DIMENSIONS PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range ADN2811ACP-CML −40°C to +85°C ADN2811ACP-CML-RL −40°C to +85°C EVAL-ADN2811-CML 7.00 BSC SQ 0.60 MAX 37 36 TOP 6.75 VIEW BSC SQ 0.50 0.40 ...
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ADN2811 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03019–0–5/04(B) Rev Page ...