ADN2811ACPZ-CML Analog Devices Inc, ADN2811ACPZ-CML Datasheet - Page 13

• Manufacturer Part Number: ADN2811ACPZ-CML
• Description: S/Rate 2.5/2.7Gbps CDR/ PA Low Power I.C
• Manufacturer: Analog Devices Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of ADN2811ACPZ-CML

• Output: CML
• Frequency - Max: 2.7GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.7GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Input: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The ADN2811 can accept any of the following reference clock
frequencies: 19.44 MHz, 38.88 MHz, 77.76 MHz at LVTTL/
LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/
LVDS levels via the REFCLKN/P inputs, independent of data
rate. The input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV
(e.g., LVPECL or LVDS) or a standard single-ended low voltage
TTL input, providing maximum system flexibility. The
appropriate division ratio can be selected using the REFSEL0/1
pins, according to Table 5. Phase noise and duty cycle of the
reference clock are not critical, and 100 ppm accuracy is
sufficient.
Table 5. Reference Frequency Selection
REFSEL
1
1
1
1
0
An on-chip oscillator to be used with an external crystal is also
provided as an alternative to using the REFCLKN/P inputs.
Details of the recommended crystal are given in Table 6.
Table 6. Required Crystal Specifications
Parameter
Mode
Frequency/Overall Stability
Frequency Accuracy
Temperature Stability
Aging
ESR
REFSEL[1..0]
00
01
10
11
XX
Applied Reference
Frequency (MHz)
19.44
38.88
77.76
155.52
REFCLKP/N Inactive. Use 19.44 MHz
XTAL oscillator on Pins XO1, XO2 (Pull
REFCLKP to VCC).
Value
Series Resonant
±100 ppm
±100 ppm
±100 ppm
50 Ω max
19.44 MHz ±100 ppm
1000
Figure 17. Transfer Function of LOL
500
Rev. B | Page 13 of 20
1
0
LOL
REFSEL must be tied to VCC when the REFCLKN/P inputs are
active, or tied to VEE when the oscillator is used. No connection
between the XO pin and REFCLK input is necessary (see
Figure 14, Figure 15, and Figure 16). Note that the crystal should
operate in series resonant mode, which renders it insensitive to
external parasitics. No trimming capacitors are required.
LOCK DETECTOR OPERATION
The lock detector monitors the frequency difference between
the VCO and the reference clock and deasserts the loss of lock
signal when the VCO is within 500 ppm of center frequency
(see Figure 17). This enables the phase loop, which pulls the
VCO frequency in the remaining amount and also acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss of lock signal is reasserted and
control returns to the frequency loop, which reacquires and
maintains a stable clock signal at the output.
The frequency loop requires a single external capacitor between
CF1 and CF2. The capacitor specification is given in Table 7.
Table 7. Recommended C
Parameter
Temperature Range
Capacitance
Leakage
Rating
500
1000
f
(ppm)
VCO
ERROR
F
Capacitor Specification
Value
−40°C to +85°C
>3.0 µF
<80 nA
>6.3 V
ADN2811