ADN2811ACPZ-CML Analog Devices Inc, ADN2811ACPZ-CML Datasheet - Page 10

• Manufacturer Part Number: ADN2811ACPZ-CML
• Description: S/Rate 2.5/2.7Gbps CDR/ PA Low Power I.C
• Manufacturer: Analog Devices Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of ADN2811ACPZ-CML

• Output: CML
• Frequency - Max: 2.7GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.7GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Input: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN2811
THEORY OF OPERATION
The ADN2811 is a delay-locked and phase-locked loop circuit
for clock recovery and data retiming from an NRZ encoded
data stream. The phase of the input data signal is tracked by two
separate feedback loops that share a common control voltage. A
high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of the
input jitter. A separate phase control loop, comprised of the
VCO, tracks the low frequency components of the input jitter.
The initial frequency of the VCO is set by yet a third loop,
which compares the VCO frequency with the reference
frequency and sets the coarse tuning voltage. The jitter tracking
phase-locked loop controls the VCO by the fine tuning control.
The delay-locked and phase-locked loops together track the
phase of the input data signal. For example, when the clock lags
input data, the phase detector drives the VCO to a higher
frequency and also increases the delay through the phase shifter.
Both of these actions serve to reduce the phase error between
the clock and data. The faster clock picks up phase while the
delayed data loses phase. Since the loop filter is an integrator,
the static phase error is driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for the frequency compensation of a second-
order phase-locked loop, and this zero is placed in the feedback
path and therefore does not appear in the closed-loop transfer
function. Jitter peaking in a conventional second-order phase-
locked loop is caused by the presence of this zero in the closed-
loop transfer function. Since this circuit has no zero in the
closed-loop transfer, jitter peaking is minimized.
The delay- and phase-locked loops together simultaneously
provide wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 12 shows that
the jitter transfer function, Z(s)/X(s), is a second-order low-pass
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means the main PLL loop has low jitter peaking (see Figure 13),
which makes this circuit ideal for signal regenerator
applications where jitter peaking in a cascade of regenerators
can contribute to hazardous jitter accumulation.
Rev. B | Page 10 of 20
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation
since the jitter transfer function, Z(s)/X(s), provides the narrow-
band jitter filtering.
The delay- and phase-locked loops contribute to overall jitter
accommodation. At low frequencies of input jitter on the data
signal, the integrator in the loop filter provides high gain to
track large jitter amplitudes with small phase error. In this case,
the VCO is frequency modulated and jitter is tracked as in an
ordinary phase-locked loop. The amount of low frequency jitter
that can be tracked is a function of the VCO tuning range. A
wider tuning range gives larger accommodation of low
frequency jitter. The internal loop control voltage remains small
for small phase errors, so the phase shifter remains close to the
center of its range, and therefore contributes little to the low
frequency jitter accommodation.
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track the input jitter. In this case,
the VCO control voltage becomes large and saturates, and the
VCO frequency dwells at one or the other extreme of its tuning
range. The size of the VCO tuning range therefore has only a
small effect on the jitter accommodation. The delay-locked loop
control voltage is now larger; thus the phase shifter takes on the
burden of tracking input jitter. The phase shifter range, in UI,
can be seen as a broad plateau on the jitter tolerance curve. The
phase shifter has a minimum range of 2 UI at all data rates.
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
INPUT
DATA
X(s)
RECOVERED
Figure 12. PLL/DLL Architecture
CLOCK
Z(s)
TRACKING ERROR TRANSFER FUNCTION
psh
e(s)
JITTER TRANSFER FUNCTION
Z(s)
X(s)
X(s)
e(s)
d/sc
=
=
s
s
2
2
cn
do
+ s
o/s
+ s
d psh
s
1
c
2
n psh
o
+
do
cn
+1