ADN2811ACPZ-CML Analog Devices Inc, ADN2811ACPZ-CML Datasheet - Page 15

• Manufacturer Part Number: ADN2811ACPZ-CML
• Description: S/Rate 2.5/2.7Gbps CDR/ PA Low Power I.C
• Manufacturer: Analog Devices Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of ADN2811ACPZ-CML

• Output: CML
• Frequency - Max: 2.7GHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 2.7GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Input: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane to both analog and
digital grounds is recommended. The VEE pins should be
soldered directly to the ground plane to reduce series
inductance. If the ground plane is an internal plane and
connections to the ground plane are made through vias,
multiple vias may be used in parallel to reduce the series
inductance, especially on Pins 33 and 34, which are the ground
returns for the output buffers.
Use of a 10 µF electrolytic capacitor between VCC and GND is
recommended at the location where the 3.3 V supply enters the
PCB. 0.1 µF and 1 nF ceramic chip capacitors should be placed
between IC power supply VCC and GND as close as possible to
the ADN2811’s VCC pins. Again, if connections to the supply
and ground are made through vias, the use of multiple vias in
parallel helps to reduce series inductance, especially on Pins 35
and 36, which supply power to the high speed CLKOUTP/N
and DATAOUTP/N output buffers. Refer to the schematic in
Figure 19 for recommended connections.
Transmission Lines
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections, including PIN,
NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN
(also REFCLKP, REFCLKN for a 155.2 MHz REFCLK). It is also
recommended that the PIN/NIN input traces are matched in
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length and that the CLKOUTP/N and DATAOUTP/N output
traces are matched in length. All high speed CML outputs,
CLKOUTP/N and DATAOUTP/N, also require 100 Ω back
termination chip resistors connected between the output pin
and VCC. These resistors should be placed as close as possible
to the output pins. These 100 Ω resistors are in parallel with
on-chip 100 Ω termination resistors to create a 50 Ω back
termination (see Figure 20).
The high speed inputs, PIN and NIN, are internally terminated
with 50 Ω to an internal reference voltage (see Figure 21). A
0.1 µF capacitor is recommended between VREF, Pin 4, and
GND to provide an ac ground for the inputs.
As with any high speed mixed-signal design, care should be
taken to keep all high speed digital traces away from sensitive
analog nodes.
Soldering Guidelines for Chip-Scale Package
The lands on the 48-lead LFCSP are rectangular. The printed
circuit board pad for these should be 0.1 mm longer than the
package land length and 0.05 mm wider than the package land
width. The land should be centered on the pad. This ensures
that the solder joint size is maximized. The bottom of the chip
scale package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to analog VCC.
If vias are used, they should be incorporated into the pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz.
copper to plug the via.
ADN2811