ADSP-21061LKSZ-176 Analog Devices Inc, ADSP-21061LKSZ-176 Datasheet - Page 43

• Manufacturer Part Number: ADSP-21061LKSZ-176
• Description: ADSP-21061L 44Hz, 3V SHARC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061LKSZ-176

• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 44MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

JTAG Test Access Port and Emulation
For JTAG Test Access Port and Emulation, see
Figure
Table 28. JTAG Test Access Port and Emulation
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = DATA47–0, ADDR31–0, RD, WR, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, CPA, DR0, DR1, TCLK0,
System Outputs = DATA47–0, ADDR31–0, MS3–0, RD, WR, SW, ACK, ADRCLK, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, CPA, FLAG3–0, TIMEXP, DT0, DT1,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, EBOOT, LBOOT, BMS, CLKIN, RESET.
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS.
26.
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
DTDO
Figure 26. JTAG Test Access Port and Emulation
Table 28
Rev. C | Page 43 of 56 | July 2007
t
1
TCK
t
t
DSYS
1
STAP
2
and
t
HTAP
t
SSYS
Min
t
t
6
7
18
4t
CK
CK
CK
ADSP-21061/ADSP-21061L
t
HSYS
5 V and 3.3 V
Max
13
18.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns