ADSP-21061LKSZ-176 Analog Devices Inc, ADSP-21061LKSZ-176 Datasheet - Page 8

• Manufacturer Part Number: ADSP-21061LKSZ-176
• Description: ADSP-21061L 44Hz, 3V SHARC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061LKSZ-176

• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 44MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21061/ADSP-21061L
Program Booting
The internal memory of the ADSP-21061 can be booted at sys-
tem power-up from either an 8-bit EPROM, or a host processor.
Selection of the boot source is controlled by the BMS (boot
memory select), EBOOT (EPROM boot), and LBOOT (host
boot) pins. 32-bit and 16-bit host processors can be used for
booting.
PORTING CODE FROM THE ADSP-21060 OR
ADSP-21062
The ADSP-21061 is pin compatible with the ADSP-21060/
ADSP-21061/ADSP-21062 processors. The ADSP-21061 pins
that correspond to the link port pins of the ADSP-21060/
ADSP-21062 are no-connects.
The ADSP-21061 is object code compatible with the
ADSP-21060/ADSP-21062 processors except for the folowing
functional elements:
On the ADSP-21061, Block 0 starts at the beginning of internal
memory, normal word address 0x0002 0000. Block 1 starts at
the end of Block 0, with contiguous addresses. The remaining
addresses in internal memory are divided into blocks that alias
into Block 1. This allows any code or data stored in Block 1 on
the ADSP-21062 to retain the same addresses on the
ADSP- 21061—these addresses will alias into the actual Block 1
of each processor.
If you develop your application using the ADSP-21062, but will
migrate to the ADSP-21061, use only the first eight columns of
each memory bank. Limit your application to 8k of instructions
or up to 16k of data in each bank of the ADSP-21062, or any
combination of instructions or data that does not exceed the
memory bank.
DEVELOPMENT TOOLS
The ADSP-21061 is supported by a complete set of
CROSSCORE
Devices emulators and VisualDSP++
ment. The same emulator hardware that supports other SHARC
processors also fully emulates the ADSP-21061.
†
‡
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
• The ADSP-21061 memory is organized into two blocks
• Link port functions are not available.
• Handshake external port DMA pins DMAR2 and DMAG2
• 2-D DMA capability of the SPORT is not available.
• The modify registers in SPORT DMA are not
with eight columns that are 4k deep per block. The
ADSP-21060/ADSP-21062 memory has 16 columns per
block.
are assigned to external port DMA Channel 6 instead of
Channel 8.
programmable.
®†
software development tools, including Analog
®‡
development environ-
Rev. C | Page 8 of 56 | July 2007
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The ADSP-21061
SHARC DSP has architectural features that improve the
efficiency of compiled C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-21061
development tools, including the color syntax highlighting in
the VisualDSP++ editor. This capability permits programmers
to:
The VisualDSP++ kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
• View mixed C/C++ and assembly code (interleaved source
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
• Control how the development tools process inputs and
• Maintain a one-to-one correspondence with the tools’
and object information)
and stacks
generate outputs
command line switches