CY28400OXC-2T Silicon Laboratories Inc, CY28400OXC-2T Datasheet
CY28400OXC-2T
Specifications of CY28400OXC-2T
Related parts for CY28400OXC-2T
CY28400OXC-2T Summary of contents
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MHz Differential Buffer for PCI Express and SATA Features • CK409 and CK410 companion buffer • Four differential 0.7V clock output pairs • OE_INV input for inverting OE, PWRDWN, and SRC_STP active levels • Individual OE controls • Low ...
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Pin Description Pin Name 2,3 SRCT_IN, SRCC_IN 6,7;9,10;20,19; DIF[T/C][2:1] & [6:5] 23,22 8,21 OE_1, OE_6 17 HIGH_BW# 15 PWRDWN 16 SRC_STP 13 SCLK 14 SDATA 26 IREF 12 PLL/BYPASS# 28 VDD_A 27 VSS_A 4 VSS 1,5,11,18,24 VDD 25 OE_INV Serial ...
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Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit Description 9 Write = 0 10 Acknowledge from slave 11:18 Command Code – 8 bits '00000000' stands for block operation 19 Acknowledge from slave 20:27 Byte Count ...
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Byte 0: Control Register 0 (continued) Bit @pup Name 5 0 Reserved 4 0 Reserved 3 0 Reserved 2 1 HIGH_BW PLL/BYPASS SRC_DIV2# Byte 1: Control Register 1 Bit @pup Name 7 1 Reserved 6 1 ...
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Byte 3: Control Register 3 Bit @pup Name Byte 4: Vendor ID Register Bit @Pup Name ...
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OE_INV PWRDWN PWRDWN—Assertion When the power-down pin is sampled as being asserted by two consecutive rising edges of DIFC, all DIFT outputs will be held high or tri-stated (depending on the state ...
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Table 4. Buffer Power-up State Machine State 0 3.3V Buffer power off 1 After 3.3V supply is detected to rise above 1.8V - 2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay [1] 2 Buffer waits for PWRDWN ...
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SRC_STP Deassertion All differential outputs that were stopped will resume normal operation in a glitch-free manner. The maximum latency from the deassertion to active outputs is between 2–6 DIFT/C clock periods (2 clocks are shown) with all DIFT/C outputs resuming ...
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SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 9. SRC_STP = Driven, PWRDWN = Driven, OE_INV = 1 SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 10. SRC_STP = Tri-state, PWRDWN = Driven, OE_INV ...
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OE Assertion All differential outputs that were tri-stated will resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2–6 DIF clock periods. In addition, DIFT clocks will be driven high within ...
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Absolute Maximum Conditions Parameter Description V Core Supply Voltage DD V Analog Supply Voltage DD_A V Input Voltage IN T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J ESD ESD Protection (Human Body Model) HBM UL-94 ...
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AC Electrical Specifications (continued) (Measured in High Bandwidth Mode) Parameter Description ΔV Vcross Variation over all edges OX V Differential Ringback Voltage RB T Time before ringback allowed STABLE V Absolute maximum input voltage MAX V Absolute minimum input voltage ...
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Switching Waveforms V = 0.525V OH VCROSS V = 0.175V OL Figure 13. Single-Ended Measurement Points for TRise and TFall V OVS V RB Figure 14. Single-ended Measurement Points for V Rev 1.0, November 21, 2006 CY28400-2 TRise (CLOCK) TFall ...
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... Skew Management Point 0.000V Figure 15. Differential (Clock-Clock#) Measurement Points (Tperiod, Duty Cycle and Jitter) Ordering Information Ordering Code Lead-free CY28400OXC-2 CY28400OXC-2T CY28400ZXC-2 CY28400ZXC-2T Package Drawing and Dimensions 28-Lead (5.3 mm) Shrunk Small Outline Package O28 Rev 1.0, November 21, 2006 T PERIOD High Duty Cycle % ...
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Thin Shrunk Small Outline Package (4.40-mm Body) Z28.173 0.65[0.025] BSC. 0.85[0.033] 0.95[0.037] 9.60[0.378] 9.80[0.386] While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or ...