CY28400OXC-2T Silicon Laboratories Inc, CY28400OXC-2T Datasheet - Page 8

no-image

CY28400OXC-2T

Manufacturer Part Number
CY28400OXC-2T
Description
Clock Buffer PCIe buffer 1in 4out
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of CY28400OXC-2T

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Rev 1.0, November 21, 2006
SRC_STP Deassertion
All differential outputs that were stopped will resume normal
operation in a glitch-free manner. The maximum latency from
the deassertion to active outputs is between 2–6 DIFT/C clock
periods (2 clocks are shown) with all DIFT/C outputs resuming
simultaneously. If the control register tri-state bit is
programmed to ‘1’ (tri-state), then all stopped DIFT outputs will
be driven high within 15 ns of SRC_STP deassertion to a
voltage greater than 200 mV.
DIFC(Free Running
DIFT(Free Running
DIFC(Free Running
DIFC(Free Running
DIFT(Free Running
DIFT(Free Running
DIFC (Stoppable)
DIFT (Stoppable)
DIFC (Stoppable)
DIFC (Stoppable)
DIFT (Stoppable)
DIFT (Stoppable)
SRC_STP
SRC_STP
SRC_STP
PWRDWN
PWRDWN
PWRDWN
Figure 8. SRC_STP = Tri-state, PWRDWN = Tri-state, OE_INV = 0
Figure 7. SRC_STP = Tri-state, PWRDWN = Driven, OE_INV = 0
Figure 6. SRC_STP = Driven, PWRDWN = Driven, OE_INV = 0
1 ms
CY28400-2
1 ms
1 ms
Page 8 of 15

Related parts for CY28400OXC-2T