CY28400OXC-2T Silicon Laboratories Inc, CY28400OXC-2T Datasheet - Page 5

• Manufacturer Part Number: CY28400OXC-2T
• Description: Clock Buffer PCIe buffer 1in 4out
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28400OXC-2T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Rev 1.0, November 21, 2006
Byte 3: Control Register 3
Byte 4: Vendor ID Register
Byte 5: Control Register 5
OE_INV Clarification
The OE_INV pin is an input strap sampled at power-on. The
functionality of this input is to set the active level polarities for
OE_1, OE_6, PWRDWN, and SRC_STP input pins. ‘Active
HIGH’ indicates the functionality of the input is asserted when
the input voltage level at the pin is high and deasserted when
the voltage level at the input is low. ‘Active LOW’ indicates that
the functionality of the input is asserted when the voltage level
at the input is low and deasserted when the voltage level at the
input pin is high. See V
cations for input voltage high and low ranges.
OE_INV
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
@Pup
@pup
@Pup
Active HIGH
Active LOW
PWRDWN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
IH
and V
IL
Active HIGH
Active LOW
in the DC Electrical Specifi-
SRC
Name
Name
Name
OE_1, OE_6
Active HIGH
Active LOW
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWRDWN Clarification
The PWRDWN pin is an asynchronous input used to shut off
all clocks cleanly and instruct the device to evoke power
savings mode. It may be active HIGH or active LOW
depending on the strapped value of the OE_INV input. The
PWRDWN pin should be asserted prior to shutting off the input
clock or power to ensure all clocks shut down in a glitch-free
manner. This signal is synchronized internal to the device prior
to powering down the clock buffer. PWRDWN is an
asynchronous input for powering up the system. When the
PWRDWN pin is asserted, all clocks will be held high or
tri-stated (depending on the state of the control register drive
mode and OE bits) prior to turning off the VCO. All clocks will
start and stop without any abnormal behavior and meet all AC
and DC parameters. This means no glitches, frequency
shifting or amplitude abnormalities among others.
Description
Description
Description
CY28400-2
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