LAN88710BMR SMSC, LAN88710BMR Datasheet - Page 23

• Manufacturer Part Number: LAN88710BMR
• Description: Ethernet ICs MII/RMII 10/100 Automot Transceiver
• Manufacturer: SMSC

Specifications of LAN88710BMR

• Ethernet Connection Type: 10BASE-T, 100BASE-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Standard Supported: IEEE802.3, IEEE802.3u
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: QFN-32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Footprint MII/RMII 10/100 Ethernet Transceiver for Automotive Applications
Datasheet
SMSC LAN88710AM/LAN88710BM
3.1.2
3.1.2.1
3.1.2.2
3.1.2.3
MAC
Converter
100BASE-TX Receive
The 100BASE-TX receive data path is shown below. Each major block is explained in the following
subsections.
100M Receive Input
The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio
transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second.
Using a 64-level quanitizer, it generates 6 digital bits to represent each sample. The DSP adjusts the
gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC
can be used.
Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates
for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,
and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1 m
and 100 m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency
pole of the isolation transformer, then the droop characteristics of the transformer will become
significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the
received data, the transceiver corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD
defined “killer packet” with no bit errors.
The 100M PLL generates multiple phases of the 125 MHz clock. A multiplexer, controlled by the timing
unit of the DSP, selects the optimum phase for sampling the data. This is used as the received
recovered clock. This clock is used to extract the serial data from the received signal.
NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then
converted to an NRZI data stream.
Converter
NRZI
A/D
Ext Ref_CLK (for RMII only)
RMII 50 MHz by 2 bits
MII 25 MHz by 4 bits
(for MII only)
RX_CLK
NRZI
or
MLT-3
Converter
MLT-3
Magnetics
MII/RMII
PLL
DATASHEET
MLT-3
125 Mbps Serial
by 4 bits
25 MHz
MLT-3
6 bit Data
23
RJ45
Decoder
4B/5B
and BLW Correction
recovery, Equalizer
MLT-3
DSP: Timing
CAT-5
25 MHz by
5 bits
Descrambler
and SIPO
Revision 1.1 (05-26-10)