MT46H16M16LFBF-6:H Micron Technology Inc, MT46H16M16LFBF-6:H Datasheet - Page 42

• Manufacturer Part Number: MT46H16M16LFBF-6:H
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 1.8V 60-Pin VFBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr
• Series: -r

Specifications of MT46H16M16LFBF-6:H

• Package: 60VFBGA
• Density: 256 Mb
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Clock Rate: 166 MHz
• Maximum Random Access Time: 6.5|5 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Package / Case: 60-VFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 16: Truth Table – Current State Bank n – Command to Bank m (Continued)
Notes 1–6 apply to all parameters in this table
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
Current State
Read (with auto
precharge)
Write (with auto
precharge)
CS#
Notes:
L
L
L
L
L
L
L
L
RAS#
H
H
H
H
L
L
L
L
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted (for example, the cur-
3. Current state definitions:
the previous state was self refresh), after
down, or a full initialization if the previous state was deep power-down).
rent state is for bank n and the commands shown are those supported for issue to bank
m, assuming that bank m is in such a state that the given command is supported). Excep-
tions are covered in the notes below.
Idle: The bank has been precharged, and
Row active: A row in the bank has been activated, and
accesses and no register accesses are in progress.
Read: A READ burst has been initiated and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated and has not yet terminated or been terminated.
3a. Both the read with auto precharge enabled state or the write with auto precharge
enabled state can be broken into two parts: the access period and the precharge period.
For read with auto precharge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with the earliest possible PRE-
CHARGE command that still accesses all of the data in the burst. For write with auto
precharge, the precharge period begins when
precharge was disabled. The access period starts with registration of the command and
ends when the precharge period (or
precharge such that when a read with auto precharge is enabled or a write with auto
precharge is enabled, any command to other banks is supported, as long as that com-
mand does not interrupt the read or write data transfer already in process. In either
case, all other related limitations apply (i.e., contention between read data and write
data must be avoided).
3b. The minimum delay from a READ or WRITE command (with auto precharge enabled)
to a command to a different bank is summarized below.
From
Command
WRITE with
Auto Precharge
CAS#
H
H
H
H
L
L
L
L
WE#
H
H
H
H
L
L
L
L
To Command
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE
ACTIVE
Command/Action
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
42
n - 1
256Mb: x16, x32 Mobile LPDDR SDRAM
was HIGH, CKE
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RP) begins. This device supports concurrent auto
t
XP has been met (if the previous state was power-
t
RP has been met.
t
n
WR ends, with
is HIGH and after
t
RCD has been met. No data bursts/
(with Concurrent Auto
©2008 Micron Technology, Inc. All rights reserved.
[1 + (BL/2)]
t
WR measured as if auto
Minimum Delay
t
Precharge)
XSR has been met (if
(BL/2)
1
1
Truth Tables
t
t
CK
CK
t
CK +
t
CK
t
WTR
Notes
7