MAX2830ETM+T Maxim Integrated Products, MAX2830ETM+T Datasheet - Page 19

• Manufacturer Part Number: MAX2830ETM+T
• Description: RF Transceiver 2.4GHz to 2.5GHz 802 .11g-b RF Transceive
• Manufacturer: Maxim Integrated Products

Specifications of MAX2830ETM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA,
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
2
3
4
5
6
7
8
9
CLOCKOUT
GN DRX LNA
GNDVCO
V
V
V
V
BYPASS
V
GNDCP
CPOUT
V
CTUNE
ANT1+
ANT2+
V
V
NAME
ANT1-
ANT2-
CCTXMX
SHDN
CCTXPA
CCXTAL
SCLK
TUNE
CCVCO
CCLNA
XTAL
RSSI
CCPLL
CCPA
DIN
CCCP
CS
B6
B7
B3
B2
B5
LD
B1
B4
______________________________________________________________________________________
LNA Supply Voltage
LNA Ground
Receiver and Transmitter Gain-Control Logic-Input Bit 6
Antenna 1. Differential Input to LNA in Rx mode. Input is internally AC-coupled and matched to 100Ω
differential. Connect directly to a 2:1 balun.
Receiver Gain-Control Logic-Input Bit 7
Supply Voltage for Second Stage of Power Amplifier
Receiver and Transmitter Gain-Control Logic-Input Bit 3
Antenna 2. Differential inputs to LNA in diversity Rx mode and to PA differential outputs in Tx mode.
Internally AC-coupled differential outputs and matched to 100Ω differential. Connect directly to a 2:1 balun.
Receiver and Transmitter Gain-Control Logic-Input Bit 2
Active-Low Shutdown and Standby Logic Input. See Table 32 for operating modes.
Supply Voltage for First-Stage of PA and PA Driver
Receiver and Transmitter Gain-Control Logic-Input Bit 5
Active-Low Chip-Select Logic Input of 3-Wire Serial Interface (see Figure 3)
RSSI, PA Power Detector or Temperature-Sensor Multiplexed Analog Output
Transmitter Upconverter Supply Voltage
Serial-Clock Logic Input of 3-Wire Serial Interface (see Figure 3)
Data Logic Input of 3-Wire Serial Interface (see Figure 3)
PLL and Registers Supply Voltage. Connect to the supply voltage to retain the register settings.
Reference Clock Buffer Output
Lock- D etect Log i c Outp ut of Fr eq uency S ynthesi zer . O utp ut hi g h i nd i cates that the fr eq uency synthesi zer i s
l ocked . Outp ut p r og r am m ab l e as C M O S or op en- d r ai n outp ut. ( S ee Tab l es 17 and 21.)
Receiver and Transmitter Gain-Control Logic-Input Bit 1
Charge-Pump Output. Connect the frequency synthesizer’s loop filter between CPOUT and TUNE (see the
Block Diagram/Typical Operating Circuit).
PLL Charge-Pump Supply Voltage
Charge-Pump Circuit Ground
Crystal Oscillator Supply Voltage
Crystal or Reference Clock Input. AC-couple a crystal or a reference clock to this analog input.
Connection for Crystal Oscillator Off-Chip Capacitors. When using an external reference clock input, leave
CTUNE unconnected.
VCO Supply Voltage
VCO Ground
VCO TUNE Input (see the Block Diagram/Typical Operating Circuit)
On-Chip VCO Regulator Output Bypass. Bypass with a 0.1µF to 1µF capacitor to GND. Do not connect
other circuitry to this point.
Receiver and Transmitter Gain-Control Logic-Input Bit 4
and Rx/Tx/Antenna Diversity Switch
FUNCTION
Pin Description
19