MAX2830ETM+T Maxim Integrated Products, MAX2830ETM+T Datasheet - Page 24

• Manufacturer Part Number: MAX2830ETM+T
• Description: RF Transceiver 2.4GHz to 2.5GHz 802 .11g-b RF Transceive
• Manufacturer: Maxim Integrated Products

Specifications of MAX2830ETM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX2830 integrates a 2-stage PA, providing
+17.1dBm of output power at 5.6% error vector magni-
tude (EVM) (54Mbps OFDM signal) in 802.11g mode
while exceeding the 802.11g spectral mask require-
ments. The first and second stage PA bias currents are
set through programming bits D2:D0 and bits D6:D3 in
Register 10 (A3:A0 = 1010), respectively. An adjustable
PA enable delay, relative to the transmitter enable (RXTX
low-to-high transition), can be set from 200ns to 7µs
through programming bits D13:D10 in Register 10 (A3:A0
= 1010).
The MAX2830 integrates a voltage-peak detector at the
PA output and before the switch to provide an analog
voltage proportional to PA output power. See the Power
Detector over Frequency and Power Detector over
Supply Voltage graphs in the Typical Operating
Characteristics . Set bits D9:D8 = 10 in Register 8 (A3:A0
= 1000) to multiplex the power-detector analog output
voltage to the RSSI output (pin 16).
The MAX2830 integrates a 20-bit sigma-delta fractional-
N synthesizer, allowing the device to achieve excellent
phase-noise performance (0.9° RMS from 10kHz to
10MHz), fast PLL settling times, and an RF frequency
step-size of 20Hz. The synthesizer includes a divide-by-
2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA,
and Rx/Tx/Antenna Diversity Switch
Table 12. Integer Divider Register (A3:A0 = 0011)
Table 13. Fractional Divider Register (A3:A0 = 0100)
24
D13:D0
D13:D8
D7:D0
______________________________________________________________________________________
BIT
BIT
Power-Amplifier Bias and Enable Delay
RECOMMENDED
RECOMMENDED
11011001100110
01111001
000000
Synthesizer Programming
6 LSBs of 20-Bit Fractional Portion of Main Divider
8-Bit Integer Portion of Main Divider. Programmable from 64 to 255.
14 MSBs of 20-Bit Fractional Portion of Main Divider
Power Detector
1 or a divide-by-2 reference frequency divider, an 8-bit
integer portion main divider with a divisor range pro-
grammable from 64 to 255, and a 20-bit fractional por-
tion main-divider. Bit D2 in Register 5 (A3:A0 = 0101)
sets the reference oscillator divider ratio to 1 or 2. Bits
D7:D0 in Register 3 (A3:A0 = 0011) set the integer por-
tion of the main divider. The 20-bit fractional portion of
the main-divider is split between two registers. The 14
MSBs of the fractional portion are set in Register 4
(A3:A0 = 0100), and the 6 LSBs of the fractional portion
of the main divider are set in Register 3 (A3:A0 = 0011).
See Tables 12 and 13.
The desired integer and fractional divider ratios can be
calculated by dividing the RF frequency (f
For nominal 802.11g/b operation, a 40MHz reference
oscillator is divided by 2 to generate a 20MHz compari-
son frequency (f
used when calculating divider ratios supporting various
reference and comparison frequencies:
See Table 14 for integer and fractional divider ratios for
802.11g/b systems using a 20MHz comparison frequency.
Fractional Divider = 0.85 x (2
LO Frequency Divider = f
Calculating Integer and Fractional Divider Ratios
Integer Divider = 121 (d) = 0111 1001 (binary)
DESCRIPTION
DESCRIPTION
= 1101 1001 1001 1001 1001
COMP
20MHz = 121.85
). The following method can be
RF
20
/ f
- 1) = 891289 (decimal)
COMP
= 2437MHz /
RF
) by f
COMP
.