MAX2830ETM+T Maxim Integrated Products, MAX2830ETM+T Datasheet - Page 25

• Manufacturer Part Number: MAX2830ETM+T
• Description: RF Transceiver 2.4GHz to 2.5GHz 802 .11g-b RF Transceive
• Manufacturer: Maxim Integrated Products

Specifications of MAX2830ETM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The crystal oscillator has been optimized to work with
low-cost crystals (e.g., Kyocera CX-3225SB). See
Figure 2. The crystal oscillator frequency can be fine
tuned through bits D6:D0 in Register 14 (A3:A0 = 1110),
which control the value of C
0.12pF steps. See the Crystal-Oscillator Offset
Frequency vs. Crystal-Oscillator Tuning Bits graph in the
Typical Operating Characteristics . The crystal oscillator
can be used as a buffer for an external reference fre-
quency source. In this case, the reference signal is AC-
coupled to the XTAL pin, and capacitors C1 and C2 are
not connected. When used as a buffer, the XTAL input
pin has to be AC-coupled. The XTAL pin has an input
impedance of 5kΩ || 4pF, (set D6:D0 = 0000000 in
Register 14 A3:A0 = 1110).
Table 14. IEEE 802.11g/b Divider-Ratio Programming Words
Figure 2. Crystal Oscillator Schematic
2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA,
FOR EXTERNAL REFERENCE CLOCK SET, C1 = C2 = OPEN
(MHz)
2412
2417
2422
2427
2432
2437
2442
2447
2452
2457
2462
2467
2472
2484
f
RF
C1
C2
CTUNE
XTAL
28
29
______________________________________________________________________________________
(f
RF
MAX2830
120.85
121.35
121.85
122.35
122.85
123.35
120.6
121.1
121.6
122.1
122.6
123.1
123.6
124.2
/ f
C
TUNE
COMP
TUNE
and Rx/Tx/Antenna Diversity Switch
1.35kΩ
)
from 0.5pF to 15.4pF in
A3:A0 = 0011, D7:D0
Crystal Oscillator
INTEGER DIVIDER
5.9kΩ
0111 1000b
0111 1000b
0111 1001b
0111 1001b
0111 1001b
0111 1001b
0111 1010b
0111 1010b
0111 1010b
0111 1010b
0111 1011b
0111 1011b
0111 1011b
0111 1100b
The reference oscillator of the MAX2830 has a divider
and a buffered output for routing the reference clock to
the accompanying baseband IC. Bit D10 in Register 14
(A3:A0 = 1110) sets the buffer divider to divide by 1 or
2, independent of the divide ratio for the reference fre-
quency provided to the PLL. Bit B9 in the same register
enables or disables the reference buffer output. See
the Clock Output waveform in the Typical Operating
Characteristics .
The PLL charge-pump output, CPOUT (pin 24), con-
nects to an external third-order, lowpass RC loop-filter,
which in turn connects to the voltage tuning input,
TUNE (pin 32), of the VCO, completing the PLL loop.
The charge-pump output sink and source current is
1mA, and the VCO tuning gain is 103MHz/V at 0.5V
tune voltage and 86MHz/V at 2.2V tune voltage. The RC
loop-filter values have been optimized for a loop band-
width of 150kHz, to achieve the desired Rx/Tx turn-
around settling time, while maintaining loop stability
and good phase noise. Refer to the MAX2830 EV kit
schematic for the recommended loop-filter component
values. Keep the line from this pin to the tune input as
short as possible to prevent spurious pickup.
The PLL features a logic lock-detect output. A logic-high
indicates the PLL is locked, and a logic-low indicates
the PLL is not locked. Bit D5 in Register 5 (A3:A0 =
0101) enables or disables the lock-detect output. Bit
A3:A0 = 0100, D13:D0
0CCCh
2666h
3666h
0666h
1666h
2666h
3666h
0666h
1666h
2666h
3666h
0666h
1666h
2666h
Reference Clock Output Divider/Buffer
FRACTIONAL DIVIDER
A3:A0 = 0011, D13:D8
Lock-Detector Output
1Ah
1Ah
1Ah
1Ah
1Ah
1Ah
1Ah
1Ah
1Ah
1Ah
1Ah
1Ah
1Ah
33h
Loop Filter
25