PIC18F14K22-E/ML Microchip Technology, PIC18F14K22-E/ML Datasheet - Page 271

• Manufacturer Part Number: PIC18F14K22-E/ML
• Description: 16KB Flash, 512bytes RAM, 256bytes EEPROM, 16MIPS, 1.8-5.5V Operation 20 QFN 4x4
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F14K22-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.2
For PIC18F1XK22/LF1XK22 devices, the WDT is
driven by the LFINTOSC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4ms and has the same stability as the
LFINTOSC oscillator.
The 4ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration register 2H. Available periods range from 4ms to
131.072 seconds (2.18 minutes). The WDT and post-
scaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits of the OSCCON register are changed or a
clock failure has occurred.
FIGURE 22-1:
 2010 Microchip Technology Inc.
Change on IRCF bits
Note 1: The CLRWDT and SLEEP instructions
All Device Resets
LFINTOSC Source
WDTPS<3:0>
2: Changing the setting of the IRCF bits of
Watchdog Timer (WDT)
clear the WDT and postscaler counts
when executed.
the OSCCON register clears the WDT
and postscaler counts.
SWDTEN
CLRWDT
WDTEN
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
128
4
Preliminary
Programmable Postscaler
PIC18F1XK22/LF1XK22
1:1 to 1:32,768
Reset
DS41365D-page 271
Wake-up
from Power
Managed Modes
WDT
Reset