S25FL128P0XMFI011 Spansion Inc., S25FL128P0XMFI011 Datasheet
S25FL128P0XMFI011
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S25FL128P0XMFI011 Summary of contents
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... Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur. ...
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... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...
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S25FL128P 128 Megabit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Bus Data Sheet (Preliminary) Distinctive Characteristics Architectural Advantages Single power supply operation – Full voltage range: 2.7 to 3.6 V read and program operations Memory Architecture ...
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Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figures Figure 2.1 16-pin Plastic Small Outline Package (SO ...
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Tables Table 5.1 S25FL128P Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block Diagram SRAM Logic July 2, 2007 S25FL128P_00_04 Array - L RD DATA PATH IO S25FL128P PS ...
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Connection Diagrams Figure 2.1 16-pin Plastic Small Outline Package (SO HOLD VCC ...
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Input/Output Descriptions Signal Name SO (Signal Data Output) PO[7–0] (Parallel Data Input/Output) SI (Serial Data Input) SCK (Serial Clock) CS# (Chip Select) HOLD# (Hold) WP#/ACC (Write Protect/Accelerated Programming GND 4. Logic Symbol July ...
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Ordering Information The ordering part number is formed by a valid combination of the following: S25FL 128 Base Ordering Part Number S25FL128P Note Package marking omits leading “S25” and speed, package, and model number form. 5.1 Valid Combinations Table ...
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Spansion SPI Modes A microcontroller can use either of its two SPI modes to control Spansion SPI Flash memory devices: CPOL = 0, CPHA = 0 (Mode 0) CPOL = 1, CPHA = 1 (Mode ...
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Device Operations All Spansion SPI devices (S25FL-P) accept and output data in bytes (8 bits at a time). 7.1 Byte or Page Programming Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program ...
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– Sector Erase (SE) – Bulk Erase (BE) – Write Disable (WRDI) – Write Status Register (WRSR) Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0 for uniform 256 KB sector product: BP3, BP2, BP1, ...
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Hold Mode (HOLD#) The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write Status Register, program or erase operation that is currently in progress. The Hold mode starts on the falling edge ...
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Table 8.2 S25FL128P Sector Address Table (Uniform 256 KB sector) Sector ...
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Table 8.3 S25FL128P Sector Address Table (Uniform 64 KB sector) (Sheet Sector Address Range 255 FF0000h FFFFFFh 254 FE0000h FEFFFFh 253 FD0000h FDFFFFh 252 FC0000h FCFFFFh 251 FB0000h FBFFFFh 250 FA0000h FAFFFFh 249 F90000h F9FFFFh 248 F80000h ...
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Table 8.3 S25FL128P Sector Address Table (Uniform 64 KB sector) (Sheet Sector Address Range 111 6F0000h 6FFFFFh 110 6E0000h 6EFFFFh 109 6D0000h 6DFFFFh 108 6C0000h 6CFFFFh 107 6B0000h 6BFFFFh 106 6A0000h 6AFFFFh 105 ...
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Parallel Mode (for 16-pin SO package only) The parallel mode provides 8 bits of input/output to increase factory production throughput at the customer manufacturing facilities. This function is recommended for increasing production throughput. Entering Parallel mode requires issuing the ...
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11. Command Definitions The host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. On the first rising edge of SCK after CS# is driven ...
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Parallel Mode In parallel mode, the maximum SCK clock frequency is 6 MHz. The device requires a single clock cycle instead of eight clock cycles to access the next data byte. The memory array output will be the same ...
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11.2 Read Data Bytes at Higher Speed (FAST_READ: 0Bh) The FAST_READ command reads data from the memory array at the frequency (f input, with a maximum speed of 104 MHz. The host system must first select ...
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Read Identification (RDID: 9Fh) 11.3.1 Serial Mode The Read Identification (RDID) instruction opcode allows the 8-bit manufacturer identification to be read, follow by two bytes of device identification. The manufacturer identification is assigned by JEDEC. The device identification is ...
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11.3.2 Parallel Mode In parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a single clock cycle instead of eight clock cycles to access the next data byte. The method of memory ...
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Read Manufacturer and Device ID (READ_ID: 90h) 11.4.1 Serial Mode The READ_ID (90h) instruction identifies the Device Manufacturer ID and the Device ID. The instruction is initiated by driving the CS# pin low and shifting in (via the SI ...
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11.4.2 Parallel Mode The maximum clock frequency allowed on the SCK input pin in parallel mode is 10 MHz. The Parallel Mode Entry command (55h) must be issued before writing the READ_ID command. Once in the ...
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Write Disable (WRDI: 04h) The Write Disable (WRDI) command (see disables the device from accepting a Write Status Register, program, or erase command. The host system must first drive CS# low, write the WRDI command, and then drive CS# ...
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Bit Status Register Bit 7 SRWD 6 Don’t Care 5 BP3 4 BP2 3 BP1 2 BP0 1 WEL 0 WIP CS Mode 3 SCK Mode 0 SI Hi-Z SO July 2, 2007 S25FL128P_00_04 ...
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Parallel Mode When the device is in Parallel Mode, the maximum SCK clock frequency is 10 MHz. The device requires a single clock cycle instead of eight clock cycles to access the next data byte. The method of memory ...
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11.8 Write Status Register (WRSR: 01h) The Write Status Register (WRSR) command changes the bits in the Status Register. A Write Enable (WREN) command, which itself sets the Write Enable Latch (WEL) in the Status Register, ...
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WP#/ACC Signal SRWD Bit Mode 1 1 Software 1 0 Protected (SPM Hardware 0 1 Protected (HPM) Note As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in ...
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CS# Mode 3 SCK Mode SCK MSB July 2, 2007 S25FL128P_00_04 ...
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Parallel Mode In parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a single clock cycle instead of eight clock cycles to access the next data byte. The memory content input method is the same ...
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11.10 Sector Erase (SE: 20h, D8h) The Sector Erase (SE) command sets all bits at all addresses within a specified sector to a logic 1. A WREN command is required prior to writing the PP command. ...
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Bulk Erase (BE: C7h, 60h) The Bulk Erase (BE) command sets all the bits within the entire memory array to logic 1s. A WREN command is required prior to writing the PP command. For 64 KB sector devices, the ...
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11.12 Deep Power Down (DP: B9h) The Deep Power Down (DP) command provides the lowest power consumption mode of the device intended for periods when the device is not in active use, and ignores ...
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Release from Deep Power Down (RES: ABh) The device requires the Release from Deep Power Down (RES) command to exit the Deep Power Down mode. When the device is in the Deep Power Down mode, all commands except RES ...
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Figure 11.20 Serial Release from Deep Power Down and Read Electronic Signature (RES) Command Sequence CS SCK Command SI Hi-Z SO 11.14.2 Parallel Mode When the device is in parallel mode, ...
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Command Definitions Operation Command READ FAST_READ Read RDID READ_ID WREN Write Control WRDI SE Erase BE Program PP RDSR Status Register WRSR Entry Parallel Mode Exit DP Power Saving RES Note For 64 KB sector devices, either command is ...
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13. Power-up and Power-down During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied and must not be driven low to select the device until V CC (see ...
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Absolute Maximum Ratings Do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device may result. These are stress ratings only and device operation at these or any other conditions beyond ...
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17. DC Characteristics This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit match the measurement conditions specified in the Test Specifications in on page 41, when ...
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AC Characteristics Symbol F SCK Clock Frequency READ command SCK SCK Clock Frequency for: F FAST_READ, RDID, READ_ID, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, SCK WRSR (Note 4) t Clock Rise Time (Slew Rate) CRT t Clock ...
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CS# t CSH SCK SI Hi-Z SO CS# SCK July 2, 2007 S25FL128P_00_04 Figure 19.1 ...
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CS# SCK SO SI HOLD# Figure 19.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 WP#/ACC CS# SCK ...
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20. Physical Dimensions 20.1 SO3 016 wide—16-pin Plastic Small Outline Package (300-mil Body Width) PACKAGE SO3 016 (inches) SO3 016 (mm) JEDEC MS-013(D)AA MS-013(D)AA SYMBOL MIN MAX MIN A 0.093 0.104 2.35 A1 0.004 0.012 0.10 ...
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WSON 8-contact ( mm) No-Lead Package D N 0.30 DIA TYP 0. TOP VIEW 2X 0. 0.05 C SEATING PLANE A1 L e/2 QUAD FLAT NO LEAD ...
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21. Revision History Section Revision 01 (January 12, 2007) Initial release. Revision 02 (March 13, 2007) Distinctive Characteristics Changed standby mode current. S25FL128P Sector Address Table Corrected addresses for sectors 0 and 32. (Uniform 64 KB ...
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... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2007 Spansion Inc. All rights reserved. Spansion combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ...