S25FL128P0XMFI011 Spansion Inc., S25FL128P0XMFI011 Datasheet - Page 32

• Manufacturer Part Number: S25FL128P0XMFI011
• Description: IC 128M CMOS 3V/104MHZ SPI BUS INTERFACE
• Manufacturer: Spansion Inc.

32
11.9.2
Parallel Mode
In parallel mode, the maximum SCK clock frequency is 10 MHz. The device requires a single clock cycle
instead of eight clock cycles to access the next data byte. The memory content input method is the same as
serial mode. The only difference is that a byte of data is input per clock cycle instead of a single bit. This
means that 256 bytes of data can be copied into the 256 byte wide page write buffer in 256 clock cycles
instead of in 2,048 clock cycles.
Notes
1. 1st Byte = “02h”.
2. 2nd Byte = Address 1, MSB first (bits 23 through 16).
3. 3rd Byte = Address 2, MSB first (bits 15 through 8).
4. 4th Byte = Address 3, MSB first (bits 7 through 0).
5. 5th Byte = first write data byte.
6. In parallel mode, the fastest access clock frequency (Fsck) is 10 MHz (SCK pin clock frequency).
7. Programming in parallel mode requires an “Parallel mode Entry” command (55h) before the program command. Once in the parallel
PO[7-0]
mode, the flash memory will not exit parallel mode until an “Exit Parallel Mode” (45h) command is given to the flash device, or upon power
down / power up sequence completion.
SCK
CS#
SI
0
1
Figure 11.15 Parallel Page Program (PP) Instruction Sequence
2
High-Z
Instruction (02h)
3
90h
4
D a t a
5
6
S25FL128P
7
S h e e t
MSB
23 22 21
8
9
Address Byte 1
10 11 12 13 14 15
20 19 18
( P r e l i m i n a r y )
17
16
15
16
Address
Byte 2
8
23 24
S25FL128P_00_04 July 2, 2007
7
Address
Byte 3
0
31
Byte
1
32 33
Byte
2
Byte
n
n
Hi-Z