SAA4956TJ NXP Semiconductors, SAA4956TJ Datasheet
SAA4956TJ
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SAA4956TJ Summary of contents
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... DATA SHEET SAA4956TJ 2.9-Mbit field memory with noise reduction Preliminary specification File under Integrated Circuits, IC02 INTEGRATED CIRCUITS 1998 Dec 08 ...
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... PACKAGE OUTLINE 13 SOLDERING 13.1 Introduction to soldering surface mount packages 13.2 Reflow soldering 13.3 Wave soldering 13.4 Manual soldering 13.5 Suitability of surface mount IC packages for wave and reflow soldering methods 14 DEFINITIONS 15 LIFE SUPPORT APPLICATIONS 16 PURCHASE OF PHILIPS I 2 Preliminary specification SAA4956TJ 2 C COMPONENTS ...
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... When this mode is enabled, reading and/or writing may begin at, or proceed from, the start address of any of the 6144 blocks. Each block is 40 words in length. Two or more SAA4956TJs can be cascaded to provide a greater storage depth or a longer delay, without the need for additional circuitry. ...
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... DD(tot DD(tot) DD DD(O) 1998 Dec 08 CONDITIONS NREN = LOW; see Fig.4 NREN = HIGH; see Fig.4 see Fig.11 see Fig.11 minimum read/write cycle outputs open DD(P) 4 Preliminary specification SAA4956TJ MIN. TYP. MAX. UNIT 150 3.0 3.3 3.6 V 3.0 3.3 3 ...
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... WRITE ADDRESS READ2 ADDRESS MEMORY ARBITRATION REFRESH ADDRESS LOGIC READ ADDRESS internal 20-WORD ( 12) refresh 20 12 clock CLOCK OSCILLATOR 20-WORD ( 12) read read control acknowledge 3 SERIAL READ CONTROLLER 25 26 SAA4956TJ write acknowledge D0 internal IE internal COUNTER COUNTER COUNTER COUNTER load read block address MGR687 ...
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... Y output bit 5 if NREN is HIGH digital output data output 10, Y output bit 6 if NREN is HIGH digital output data output 11, Y output bit 7 if NREN is HIGH ground ground for output circuits digital input noise reduction enable 6 Preliminary specification SAA4956TJ DESCRIPTION C-bus ...
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... RSTW needs to stay LOW for a single SWCK cycle before another reset write operation can take place. If RSTW is HIGH for 1024 SWCK write clock cycles while WE is HIGH, the SAA4956TJ will enter a built-in test mode. 7.1.1.2 The SAA4956TJ will enter random write block access ...
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... SWCK. A LOW level on IE will prevent the data being written into memory and existing data will not be overwritten (write mask function; see Fig.10). The IE set- and hold (t ) times are referenced to the su(IE) h(IE) positive edge of SWCK (see Fig.9). 8 Preliminary specification SAA4956TJ ) times are referenced h(WE) ...
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... Random read block access mode The SAA4956TJ will enter random read block access mode if the following signal sequence is applied to control inputs RE and OE during the first four SWCK write clock cycles after a reset read (see Fig.13): 1 ...
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... The SAA4956TJ incorporates a test mode not intended for customer use and RSTW are held HIGH continuously for 1024 SWCK clock cycles, the SAA4956TJ will enter test mode. It will exit test mode LOW for a single SWCK cycle or if RSTW is LOW for 2 SWCK clock cycles. ...
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... Preliminary specification data input D11 (Y7 (Y0) 8 new Y delta Y LOW-PASS FILTER 1 unfiltered LF delta Y ABS/LIMITER LOW-PASS FILTER C-bus control: lumafix Klumafix Kluma LUT 2 I C-bus control: noise_shape NOISE SHAPE D to memory D11 (Y7 (Y0) SAA4956TJ D-field delay D11 (Y7 (Y0) 8 old Y HF delta Y processed Y 8 MGR689 ...
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... Table 1 Digital input and output bus format Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 2 C-bus controls: U07 U06 V07 V06 12 Preliminary specification SAA4956TJ 2 C-bus control: 2 C-bus control: Klumatochroma). R EFORMATTING AND FORMATTING 2 C-bus control: DPCMin, DPCMout) if the 2 C-bus control FORMAT Y17 Y27 Y37 Y16 Y26 ...
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... The possible fixed K-factor values of the I variables Klumafix and Kchromafix are described in Table 3. Table 3 Settings of fixed K-factor values Klumafix/Kchromafix HEX 2 C-bus controls GAIN 128 Preliminary specification SAA4956TJ 2 C-bus-controls smaller C-bus variable 2 C-bus control K-factor DECIMAL ...
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... I C-bus interface 2 The I C-bus interface in the SAA4956TJ is used in a receive mode. The standardized bus frequencies of both 100 kHz and 400 kHz can be dealt with slave receiver, the SAA4956TJ provides 8 registers for storing commands and data. These registers are accessed via so-called subaddresses. A subaddress can be thought pointer to an internal memory location ...
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... HIGH: demo mode is activated with noise reduction only at the right screen side 0 if HIGH: disables internal self-refresh to allow T for PAN- HIGH: synchronizes the noise reduction via RSTW (split_screen and DPCM not possible). Otherwise sync is line related detected cycle LOW followed by a HIGH cycle. 15 Preliminary specification SAA4956TJ FUNCTION weight ...
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... Human body model: equivalent to discharging a 100 pF capacitor through a 1500 9 THERMAL CHARACTERISTICS SYMBOL R thermal resistance from junction to ambient th(j-a) 1998 Dec 08 CONDITIONS DD( DD( DD( DD(O) note 1 note 2 PARAMETER 16 Preliminary specification SAA4956TJ MIN. MAX. 0.5 +5 0.5 +5 0.5 +5.5 0.5 +5 3.3 V 0.5 +3.8 DD(P) 0 3.3 V 0.5 +3.8 DD(P) 200 0.5 +0.5 50 750 ...
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... DD( MHz DD( MHz 4 MHz MHz NREN = LOW; see Fig.4 NREN = HIGH; see Fig.4 see Fig.4 see Fig.4 17 Preliminary specification SAA4956TJ (1) MIN. TYP. MAX. 3.0 3.3 3.6 V 3.0 3.3 3.6 V 3.0 3 0.3 V DD(P) 0.5 +0.8 ...
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... IH 18 Preliminary specification (1) MIN. TYP 3.3 V, all voltages referenced to GND. See Fig.1 2 C-bus and how to use it” (order number of the rising edge of SWCK. They are valid for the of the rising edge of SRCK. They are valid for the SAA4956TJ MAX. UNIT ...
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... T cy(SWCK) SWCK t w(SWCKH) t w(SWCKL) RSTW D0 to D11 Fig.5 Write cycle timing diagram (reset write with WE LOW). 1998 Dec h(RSTW) t su(RSTW) t h(RSTW Fig.4 Write cycle timing diagram (reset write). disable Preliminary specification SAA4956TJ su(RSTW) t su( MGK677 disable 1 1 MGK678 ...
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... Fig.7 IE controlled entry sequence of the random write block access mode. 1998 Dec 08 serial input of write block address (13 SWCK) random write block address serial input of write block address (13 SWCK) random write block address 20 Preliminary specification SAA4956TJ write latency write data (minimum 18 SWCK ...
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... Fig.9 Write cycle timing diagram (input enable = write mask operation). 1998 Dec 08 N disable t h(WE) t w(WEL) t su(D) t h(D) N Fig.8 Write cycle timing diagram (write enable). disable N t h(IE) t w(IEL) t su( Preliminary specification SAA4956TJ disable h(WE) t su(WE MGK681 disable h(IE) t su(IE MGK682 ...
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... Philips Semiconductors 2.9-Mbit field memory with noise reduction N N handbook, full pagewidth SWCK D11 N N RSTW SRCK OE RE new Q0 to Q11 N RSTR 1998 Dec new old high Fig.10 Write mask operation. 22 Preliminary specification SAA4956TJ old new new new MGK683 ...
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... T cy(SRCK) SRCK t w(SRCKH) t w(SRCKL) RSTR t ACC Q0 to Q11 Fig.12 Read cycle timing diagram (reset read with RE LOW). 1998 Dec h(RSTR) t su(RSTR) t h(RSTR Fig.11 Read cycle timing diagram (reset read Preliminary specification SAA4956TJ su(RSTR MGK684 ACC 1 MGK685 ...
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... SRCK t su(RE Q11 RSTR 1998 Dec 08 serial input of read block address (13 SRCK) random read block address h(RE) t w(REL) N Fig.14 Read cycle timing diagram (read enable). 24 Preliminary specification SAA4956TJ read latency read data (minimum 20 SRCK LSB at block address: read data h(RE) ...
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... Philips Semiconductors 2.9-Mbit field memory with noise reduction N handbook, full pagewidth SRCK t su(OE Q11 RSTR 1998 Dec 08 disable disable t h(OE) t w(OEL) t dis(Q) high-Z N Fig.15 Read cycle timing diagram (output enable). 25 Preliminary specification SAA4956TJ h(OE) t su(OE) t ACC t en( MGK688 ...
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... SWCK RSTW WE and D11 SRCK RSTR RE and OE high Q11 1998 Dec new new new minimum number of SWCK cycles delay to get new data Fig.16 New data access. 26 Preliminary specification SAA4956TJ new new new new new new ...
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... SWCK RSTW WE and D11 SRCK RSTR RE and OE high Q11 1998 Dec new new new maximum number of SWCK cycles delay to get old data Fig.17 Old data access. 27 Preliminary specification SAA4956TJ new new new old new ...
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... SWCK 26 Q0 (V0 (V0) to SAA4956TJ Q11 (Y7) D11 (Y7 Fig.18 Cascade operation (signal connections new new 1 2 old old 1 2 Fig.19 Cascade operation (timing waveforms). 28 Preliminary specification SAA4956TJ RSTR 25 16 SRCK (V0) to SAA4956TJ Q11 (Y7 MGR690 new new new old old old data outputs ...
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... SWC 15 47 RSTW 17 SAA4956TJ HRD 68 Fig.20 Application diagram. 29 Preliminary specification +3 17, 18, 19, 75, 80 23, 25, 29, RST 46 D11 45 D10 SAA4977H YOUT UOUT 76 VOUT 74 1 SDA SCL 2 HDFL 16, 21, 27, 31, 72 VDFL 33, 65, 73, 10, 12, 77, 78 13, 64, 66 n.c. SRC DISPLAY PLL MBK914 SAA4956TJ ...
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... Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT449-1 1998 Dec scale (1) ( 0.51 0.81 0.32 26.2 10.3 1.27 0.38 0.66 0.18 25.9 10.0 REFERENCES JEDEC EIAJ MS027 30 Preliminary specification SAA4956TJ detail 11.30 1.4 9.4 0.18 0.18 11.05 1.1 EUROPEAN PROJECTION SOT449 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 31 Preliminary specification SAA4956TJ ...
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... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1998 Dec 08 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 32 Preliminary specification SAA4956TJ (1) REFLOW suitable suitable suitable suitable suitable ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 1998 Dec 08 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 33 Preliminary specification SAA4956TJ 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors 2.9-Mbit field memory with noise reduction 1998 Dec 08 NOTES 34 Preliminary specification SAA4956TJ ...
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... Philips Semiconductors 2.9-Mbit field memory with noise reduction 1998 Dec 08 NOTES 35 Preliminary specification SAA4956TJ ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, ...