SAA4956TJ NXP Semiconductors, SAA4956TJ Datasheet - Page 18

• Manufacturer Part Number: SAA4956TJ
• Manufacturer: NXP Semiconductors

Specifications of SAA4956TJ

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
Notes
1. Typical values are valid for T
2. The AC characteristics are in accordance with the I
3. The write cycle timing set-up and hold times are related to V
4. The read cycle timing set-up and hold times are related to V
5. Disable times specified are from the initiating edge until the output is no longer driven by the memory. Disable times
1998 Dec 08
t
t
t
t
t
t
t
t
t
t
t
Read cycle timing; note 4
t
t
t
t
T
t
t
t
t
t
t
t
t
t
t
t
su(D)
h(D)
su(RSTW)
h(RSTW)
su(WE)
h(WE)
W(WEL)
su(IE)
h(IE)
W(IEL)
t
ACC
en(Q)
dis(Q)
h(Q)
W(SRCKH)
W(SRCKL)
su(RSTR)
h(RSTR)
su(RE)
h(RE)
W(REL)
su(OE)
h(OE)
W(OEL)
t
SYMBOL
cy(SRCK)
2.9-Mbit field memory with noise reduction
for configuration.
400 kHz). Information about the I
9398 393 40011).
specified LOW and HIGH-level input voltages (V
specified LOW and HIGH-level input voltages (V
in parallel with a 218
are measured by observing the output waveforms. Low values of load resistor and capacitor have to be used to
obtain a short time constant.
set-up time data inputs (D0 to D11) see Fig.4
hold time data inputs (D0 to D11)
set-up time RSTW
hold time RSTW
set-up time WE
hold time WE
WE LOW pulse width
set-up time IE
hold time IE
IE LOW pulse width
transition time (rise and fall)
access time after SRCK
output enable time after SRCK
output disable time after SRCK
output hold time after SRCK
SRCK cycle time
HIGH-level pulse width of SRCK
LOW-level pulse width of SRCK
set-up time RSTR
hold time RSTR
set-up time RE
hold time RE
LOW-level pulse width of RE
set-up time OE
hold time OE
LOW-level pulse width of OE
transition time (rise and fall)
PARAMETER
resistor to 1.31 V.
amb
2
= 25 C, V
C-bus can be found in the brochure “The I
DD
= V
see Fig.4
see Fig.4
see Fig.4
see Fig.8
see Fig.8
see Fig.8
see Fig.9
see Fig.9
see Fig.9
see Fig.4
see Fig.11
see Fig.15
note 5; see Fig.15
see Fig.11
see Fig.11
see Fig.11
see Fig.11
see Fig.11
see Fig.11
see Fig.14
see Fig.14
see Fig.14
see Fig.15
see Fig.15
see Fig.15
see Fig.11
IL
IL
DD(O)
and V
and V
2
C-bus specification for fast mode (clock frequency maximum
CONDITIONS
18
= V
IH
IH
). The load on each output is a 30 pF capacitor to ground
).
DD(P)
IL
IL
of the rising edge of SRCK. They are valid for the
of the rising edge of SWCK. They are valid for the
= 3.3 V, all voltages referenced to GND. See Fig.1
2
5
3
5
3
5
3
8
5
3
8
3
26
7
7
5
3
5
3
9
5
3
9
C-bus and how to use it” (order number
MIN.
3
3
TYP.
(1)
Preliminary specification
30
21
21
12
30
SAA4956TJ
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT