SAA4956TJ NXP Semiconductors, SAA4956TJ Datasheet - Page 14

• Manufacturer Part Number: SAA4956TJ
• Manufacturer: NXP Semiconductors

Specifications of SAA4956TJ

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Philips Semiconductors
7.2.5
If the noise shaping is activated possible shadow picture
information in the chrominance and the luminance path,
resulting from a low K-factor value, will be eliminated.
The noise shaping function can be switched off by means
of the I
applied to show the effect.
7.3
The I
receive mode. The standardized bus frequencies of both
100 kHz and 400 kHz can be dealt with.
As a slave receiver, the SAA4956TJ provides 8 registers
for storing commands and data. These registers are
accessed via so-called subaddresses. A subaddress can
be thought of as a pointer to an internal memory location.
It is allowed to send one data byte or more data bytes per
transmission to the SAA4956TJ. In this event, the
subaddress is automatically incremented after each data
byte, resulting in storing the sequence of data bytes at
successive register locations, starting at SUBADDRESS.
A transmission can start at any valid subaddress. Each
data byte is acknowledged with ACK (acknowledge).
Table 4 I
Table 5 Description of bits used in Table 4
1998 Dec 08
S
S
SLAVE ADDRESS
0
ACK
SUBADDRESS
DATA
P
2.9-Mbit field memory with noise reduction
2
C-bus interface in the SAA4956TJ is used in a
SLAVE ADDRESS
2
I
2
C-bus control. Subregister noise_shape = 0 is
C-bus interface
N
2
OISE SHAPE
C-bus control; slave address, subaddress and data format
BIT
0
START condition
7-bit device address: 1011 111 (last bit is LSB)
data direction bit (write to device)
acknowledge
address of register to write to
data byte to be written into register
STOP condition
ACK
SUBADDRESS
14
There is no ‘wrap around’ of subaddresses. Commands
and data are processed as soon as they have been
completely received. Data patterns sent to the various
subaddresses are not checked for being illegal or not at
that address. Detection of a STOP condition without a
preceding acknowledge bit is regarded as a bus error.
The last operation will not then be executed. Invalid
subaddresses are not acknowledged.
The default I
the state of the NREN pin from LOW to HIGH during
clocking of the SWCK and SCL pins. This can be realized
for example by delaying the NREN signal with an
RC-circuit for 1 second during the power-up sequence.
This is necessary to give the circuit a minimum of
20 cycles of SCL and 100 cycles of SWCK after all input
signals are stabilized.
ACK
FUNCTION
2
C-bus settings can be loaded by changing
DATA
ACK
...
Preliminary specification
SAA4956TJ
DATA
ACK
P