LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 64

• Manufacturer Part Number: LPC47M107S-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M107S-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Interrupt Enable Register
Interrupt Identification Reg.
FIFO Control
Line Control Reg.
MODEM Control Reg.
Line Status Reg.
MODEM Status Reg.
TXD1, TXD2
INTRPT (RCVR errs)
INTRPT (RCVR Data Ready)
INTRPT (THRE)
OUT2B
RTSB
DTRB
OUT1B
RCVR FIFO
XMIT FIFO
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
ADDR = 6
ADDR = 7
ADDR = 0
ADDR = 1
DLAB = 1
REGISTER ADDRESS*
DLAB = 1
REGISTER/SIGNAL
Table 32 - Register Summary for an Individual UART Channel
Receive Buffer Register (Read Only)
Transmitter Holding Register (Write
Only)
Interrupt Enable Register
Interrupt Ident. Register (Read Only)
FIFO Control Register (Write Only)
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
Scratch Register (Note 4)
Divisor Latch (LS)
Divisor Latch (MS)
Table 31 - Reset Function
REGISTER NAME
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET/Read LSR
RESET/Read RBR
RESET/ReadIIR/Write THR
RESET
RESET
RESET
RESET
RESET/
FCR1*FCR0/_FCR0
RESET/
FCR1*FCR0/_FCR0
RESET CONTROL
Page 64
REGISTER
SYMBOL
(Note 7)
MCR
MSR
RBR
THR
FCR
SCR
DLM
LCR
LSR
DDL
IER
IIR
All bits low
Bit 0 is high; Bits 1 - 7 low
All bits low
All bits low
All bits low
All bits low except 5, 6 high
Bits 0 - 3 low; Bits 4 - 7 input
High
Low
Low
Low
High
High
High
High
All Bits Low
All Bits Low
Bit 8
Data Bit 0
(Note 1)
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERDAI)
"0" if
Interrupt
Pending
FIFO Enable RCVR FIFO
Word
Length
Select Bit 0
(WLS0)
Data
Terminal
Ready
(DTR)
Data Ready
(DR)
Delta Clear
to Send
(DCTS)
Bit 0
Bit 0
BIT 0
RESET STATE
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register Empty
Interrupt
(ETHREI)
Interrupt ID Bit
Reset
Word Length
Select Bit 1
(WLS1)
Request to
Send (RTS)
Overrun Error
(OE)
Delta Data Set
Ready (DDSR)
Bit 1
Bit 1
Bit 9
BIT 1