LPC47M107S-MS Standard Microsystems (SMSC), LPC47M107S-MS Datasheet - Page 77

• Manufacturer Part Number: LPC47M107S-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M107S-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Software Constraints
Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero.
Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read.
EPP 1.7 Write
The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The
chip inserts wait states into the I/O write cycle when nWAIT is active low during the EPP cycle. This can be used to
extend the cycle time. The write cycle can complete when nWAIT is inactive high.
Write Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
EPP 1.7 Read
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states
into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The
read cycle can complete when nWAIT is inactive high.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
8.
9.
The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE.
The host initiates an I/O write cycle to the selected EPP register.
The chip places address or data on PData bus.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE
signal is valid.
If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts nWAIT or a time-
out occurs.
The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the internal data
bus for the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus.
The host initiates an I/O read cycle to the selected EPP register.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal
is valid.
If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts nWAIT or a
time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the
cycle.
The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
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