PDIUSBD12PWAA STEricsson, PDIUSBD12PWAA Datasheet - Page 16

• Manufacturer Part Number: PDIUSBD12PWAA
• Manufacturer: STEricsson

Specifications of PDIUSBD12PWAA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CD00222704
Product data sheet
11.3.1 Read Interrupt register
11.3 Data flow commands
Table 7.
Data flow commands are used to manage the data transmission between USB endpoints
and the external microcontroller. Much of the data flow is initiated using an interrupt to the
microcontroller. The microcontroller utilizes these commands to access and determine
whether endpoint FIFOs have valid data.
Code (Hex) — F4
Transaction — read 2 B
Bit
7
6
5
4
3
2
1 to 0
Symbol
ENDPOINT INDEX 5
INTERRUPT ENABLE
ENDPOINT INDEX 4
INTERRUPT ENABLE
INTERRUPT PIN MODE
AUTO RELOAD
DMA DIRECTION
DMA ENABLE
DMA BURST
Set DMA command: bit allocation
Rev. 12 — 8 April 2010
Description
Logic 1 allows an interrupt to be generated whenever the
endpoint buffer is validated (see
Normally turned off for the DMA operation to reduce
unnecessary CPU servicing.
Logic 1 allows an interrupt to be generated whenever the
endpoint buffer contains a valid packet. Normally turned off
for the DMA operation to reduce unnecessary CPU
servicing.
Logic 0 signifies a normal interrupt pin mode in which an
interrupt is generated as a logical OR of all the bits in
interrupt registers. Logic 1 signifies that the interrupt will
occur when SOF clock is seen on the upstream USB bus.
The other normal interrupts are still active.
When this bit is set to logic 1, the DMA operation will
automatically restart.
This bit determines the direction of data flow during a DMA
transfer. Logic 1 means from the external shared memory to
the PDIUSBD12 (DMA write); logic 0 means from the
PDIUSBD12 to the external shared memory (DMA read).
Writing logic 1 to this bit will start the DMA operation through
the assertion of pin DMREQ. The main endpoint buffer must
be full (for DMA read) or empty (for DMA write), before
DMREQ is asserted. In single cycle DMA mode, the
DMREQ is deactivated on receiving DMACK_N. In burst
mode DMA, the DMREQ is deactivated after the number of
burst is exhausted. It is then asserted again for the next
burst. This process continues until EOT_N is asserted
together with DMACK_N and either RD_N or WR_N, which
will reset this bit to logic 0 and terminate the DMA operation.
The DMA operation can also be terminated by writing logic 0
to this bit.
Selects the burst length for DMA operation:
00 Single-cycle DMA
01 Burst (4-cycle) DMA
10 Burst (8-cycle) DMA
11 Burst (16-cycle) DMA
USB peripheral controller with parallel bus
Section 11.3.8
PDIUSBD12
© ST-ERICSSON 2010. All rights reserved.
command).
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