PDIUSBD12PWAA STEricsson, PDIUSBD12PWAA Datasheet - Page 17

• Manufacturer Part Number: PDIUSBD12PWAA
• Manufacturer: STEricsson

Specifications of PDIUSBD12PWAA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CD00222704
Product data sheet
This command indicates the origin of an interrupt. The endpoint interrupt bits (bits 0 to 5)
are cleared by reading the Endpoint Last Transaction Status register through Read Last
Transaction Status command. The other bits are cleared after reading Interrupt registers.
Table 8.
Bit Symbol
7
6
Fig 9.
Fig 10. Interrupt register, byte 2: bit allocation
SUSPEND CHANGE
BUS RESET
For bit allocation, see
Interrupt register, byte 1: bit allocation
DMA EOT: This bit signifies that the DMA operation is completed.
Read Interrupt register, byte 1: bit allocation
Rev. 12 — 8 April 2010
0 0
7 6 5 4 3 2
Description
When the PDIUSBD12 does not receive three SOFs, it will go into the
suspend state and the SUSPEND CHANGE bit will be HIGH. Any
change to the suspend or awake state will set this bit to HIGH and
generate an interrupt.
After a bus reset, an interrupt will be generated and this bit will be
logic 1. A bus reset is identical to a hardware reset through the
RESET_N pin, except a bus reset generates an interrupt notification
and the device is enabled at default address 0.
Table
7 6 5 4 3 2
X X
0 0
8.
X X
0 0
X X
0
1
0
0
1
X
USB peripheral controller with parallel bus
Power-on value
CONTROL OUT ENDPOINT
CONTROL IN ENDPOINT
ENDPOINT 1 OUT
ENDPOINT 1 IN
MAIN OUT ENDPOINT
MAIN IN ENDPOINT
BUS RESET
SUSPEND CHANGE
0
0
Power-on value
DMA EOT
reserved
004aaa802
004aaa803
PDIUSBD12
© ST-ERICSSON 2010. All rights reserved.
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