ISP1183BSTM STEricsson, ISP1183BSTM Datasheet - Page 20

• Manufacturer Part Number: ISP1183BSTM
• Manufacturer: STEricsson

Specifications of ISP1183BSTM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Compliant

ISP1183_3
Product data sheet
10.4.1.1 DMA Counter register
10.4.1.2 Short packet
10.4.1 Bulk endpoints
10.4 EOT conditions
A DMA transfer to or from a bulk endpoint can be terminated by any of the following
conditions (for bit names, see the DMA Function and Scratch register in
DMA Configuration register in
An End-Of-Transfer (EOT) from the DMA Counter register is enabled by setting
bit CNTREN in the DMA Configuration register. The ISP1183 has a 16-bit DMA Counter
register, which specifies the number of bytes to be transferred. When DMA is enabled
(DMAEN = 1), the internal DMA counter is loaded with the value from the DMA Counter
register. When the internal counter completes the transfer as programmed in the DMA
counter, an EOT condition is generated and the DMA operation stops.
Normally, the transfer byte count must be set though a control endpoint before any DMA
transfer occurs. When a short packet has been enabled as EOT indicator (SHORTP = 1),
the transfer size is determined by the presence of a short packet in data. This mechanism
permits the use of a fully autonomous data transfer protocol.
When reading from an OUT endpoint, reception of a short packet at an OUT token will
stop the DMA operation after transferring the data bytes of this packet.
Fig 10. ISP1183 in DACK-only DMA mode
•
•
•
The DMA transfer completes as programmed in the DMA Counter register
(CNTREN = 1).
A short packet is received on an enabled OUT endpoint (SHORTP = 1).
DMA operation is disabled by clearing bit DMAEN.
ISP1183
DATA[7:0]
DREQ
DACK
Rev. 03 — 20 January 2009
Table
RAM
32):
Low-power USB Peripheral Controller with DMA
DREQ_N
DACK_N
RD_N
WR_N
CONTROLLER
DMA
HLDA
HRQ
HRQ
HLDA
© ST-NXP Wireless 2009. All rights reserved.
CPU
004aaa292
Table 30
ISP1183
and the
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