ISP1183BSTM STEricsson, ISP1183BSTM Datasheet - Page 39

• Manufacturer Part Number: ISP1183BSTM
• Manufacturer: STEricsson

Specifications of ISP1183BSTM

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Compliant

Table 39.
ISP1183_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Lock register: bit allocation
12.4.2 Unlock Device (B0h)
15
W
W
1
7
0
Table 38.
This command unlocks the ISP1183 from write-protection mode after a resume. In the
suspend state, all registers and FIFOs are write-protected to prevent data corruption by
external devices during a resume. Also, the register access for reading is possible only
after the Unlock Device command is executed.
After waking up from the suspend state, firmware must unlock registers and FIFOs using
this command, by writing the unlock code (AA37h) into the Lock register (8-bit bus: lower
byte first). The bit allocation of the Lock register is given in
Code: B0h — unlock the device
Transaction — write 2 bytes (unlock code)
Error code
(binary)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
14
W
W
0
6
0
Transaction error codes
Description
no error
PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0
PID unknown; encoding is valid, but PID does not exist
unexpected packet; packet is not of the expected type (token, data, or
acknowledge), or is a SETUP token to a non-control endpoint
token CRC error
data CRC error
time-out error
babble error
unexpected end-of-packet
sent or received NAK (Not AcKnowledge)
sent stall; a token was received, but the endpoint was stalled
overflow; the received packet was larger than the available buffer space
sent empty packet (ISO only)
bit stuffing error
sync error
wrong (unexpected) toggle bit in DATA PID; data was ignored
13
W
W
1
5
1
Rev. 03 — 20 January 2009
UNLOCKH[7:0] = AAh
UNLOCKL[7:0] = 37h
12
W
W
0
4
1
Low-power USB Peripheral Controller with DMA
11
W
W
1
3
0
10
W
W
0
2
1
Table
39.
© ST-NXP Wireless 2009. All rights reserved.
W
W
9
1
1
1
ISP1183
W
W
8
0
0
1
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