ISP1181BBS,551 NXP Semiconductors, ISP1181BBS,551 Datasheet - Page 8

• Manufacturer Part Number: ISP1181BBS,551
• Manufacturer: NXP Semiconductors

Specifications of ISP1181BBS,551

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Compliant

ISP1181B_3
Product data sheet
Table 2.
Symbol
DATA5
DATA4
DATA3
DATA2
DATA1
GND
V
AD0
A0
RD
WR
ALE
CS
RESET
CLKOUT
CC(3.3)
[1]
Pin description
Pin
TSSOP48
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Rev. 03 — 23 January 2009
…continued
HVQFN48
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Type
I/O
I/O
I/O
I/O
I/O
-
-
I/O
I
I
I
I
I
I
O
Description
bit 5 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 4 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 3 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 2 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
bit 1 of D[15:0]; bidirectional data line
(slew-rate controlled output, 4 mA)
ground supply
supply voltage (3.0 V to 3.6 V); leave this pin
unconnected when using V
multiplexed bidirectional address and data
line; represents address A0 or bit 0 of D[15:0]
in conjunction with input ALE; level-sensitive
input or slew-rate controlled output (4 mA)
Address phase: a HIGH-to-LOW transition on
input ALE latches the level on this pin as
address A0 (1 = command, 0 = data)
Data phase: during reading this pin outputs bit
D[0]; during writing the level on this pin is
latched as bit D[0]
address input; selects command (A0 = 1) or
data (A0 = 0); in a multiplexed address/data
bus configuration this pin is not used and must
be tied LOW (connect to GND)
read strobe input
write strobe input
address latch enable input; a HIGH-to-LOW
transition latches the level on pin AD0 as
address information in a multiplexed
address/data bus configuration; must be tied
LOW (connect to GND) for a separate
address/data bus configuration
chip select input
reset input (Schmitt trigger); a LOW level
produces an asynchronous reset; connect to
V
programmable clock output (2 mA)
CC
Full-speed USB peripheral controller
for power-on reset (internal POR circuit)
© ST-NXP Wireless 2009. All rights reserved.
ISP1181B
CC
= 5.0 V
7 of 72