CY8C5386LTI-005 Cypress Semiconductor Corp, CY8C5386LTI-005 Datasheet - Page 51

• Manufacturer Part Number: CY8C5386LTI-005
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5386LTI-005

• Lead Free Status / RoHS Status: Compliant

8.4 Opamps
The CY8C53 family of devices contain two general purpose
opamps.
Figure 8-5. Opamp
The opamp is uncommitted and can be configured as a gain
stage or voltage follower on external or internal signals.
See
can all be connected to the internal global signals and monitored
with an ADC, or comparator. The configurations are imple-
mented with switches between the signals and GPIO pins.
Figure 8-6. Opamp Configurations
Document Number: 001-55035 Rev. *F
Internal Bus
Global Bus
Global Bus
To Internal Signals
Analog
Analog
Analog
Figure
VREF
GPIO
GPIO
Vin
8-6. In any configuration, the input and output signals
Vn
Vp
c) Internal Uncommitted
b) External Uncommitted
a) Voltage Follower
Opamp
Opamp
Opamp
Opamp
Opamp
Opamp
=
Analog Switch
GPIO Pin
Vout to GPIO
Vp to GPIO
Vn to GPIO
Vout to Pin
Vout to Pin
PRELIMINARY
GPIO
The opamp has three speed modes, slow, medium, and fast. The
slow mode consumes the least amount of quiescent power and
the fast mode consumes the most power. The inputs are able to
swing rail-to-rail. The output swing is capable of rail-to-rail
operation at low current output, within 50 mV of the rails. When
driving high current loads (about 25 mA) the output voltage may
only get within 500 mV of the rails.
8.5 Programmable SC/CT Blocks
The CY8C53 family of devices contains two switched
capacitor/continuous time (SC/CT) blocks in a device. Each
switched capacitor/continuous time block is built around a single
rail-to-rail high bandwidth opamp.
Switched capacitor is a circuit design technique that uses capac-
itors plus switches instead of resistors to create analog functions.
These circuits work by moving charge between capacitors by
opening and closing different switches. Nonoverlapping in phase
clock signals control the switches, so that not all switches are ON
simultaneously.
The PSoC Creator tool offers a user friendly interface, which
allows you to easily program the SC/CT blocks. Switch control
and clock phase control configuration is done by PSoC Creator
so users only need to determine the application use parameters
such as gain, amplifier polarity, vref connection, and so on.
The same opamps and block interfaces are also connectable to
an array of resistors which allows the construction of a variety of
continuous time functions.
The opamp and resistor array is programmable to perform
various analog functions including
8.5.1 Naked Opamp
The Naked Opamp presents both inputs and the output for
connection to internal or external signals. The opamp has a unity
gain bandwidth greater than 6.0 MHz and output drive current up
to 650 µA. This is sufficient for buffering internal signals (such as
DAC outputs) and driving external loads greater than 7.5 kohms.
8.5.2 Unity Gain
The Unity Gain buffer is a Naked Opamp with the output directly
connected to the inverting input for a gain of 1.00. It has a -3 dB
bandwidth greater than 6.0 MHz.
8.5.3 PGA
The PGA amplifies an external or internal signal. The PGA can
be configured to operate in inverting mode or noninverting mode.
The PGA function may be configured for both positive and
negative gains as high as 50 and 49 respectively. The gain is
adjusted by changing the values of R1 and R2 as illustrated in
Figure
Naked Operational Amplifier - Continuous Mode
Unity-Gain Buffer - Continuous Mode
Programmable Gain Amplifier (PGA) - Continuous Mode
Transimpedance Amplifier (TIA) - Continuous Mode
Up/Down Mixer - Continuous Mode
Sample and Hold Mixer (NRZ S/H) - Switched Cap Mode
First Order Analog to Digital Modulator - Switched Cap Mode
PSoC
8-7. The schematic in
®
5: CY8C53 Family Data Sheet
Figure 8-7
shows the configuration
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