STPCE1HEBIE STMicroelectronics, STPCE1HEBIE Datasheet - Page 2

• Manufacturer Part Number: STPCE1HEBIE
• Manufacturer: STMicroelectronics

Specifications of STPCE1HEBIE

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 2.45/3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.7/3.6V
• Package Type: BGA
• Screening Level: Industrial
• Pin Count: 388
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

2/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
X86 Processor core
Fully static 32-bit 5-stage pipeline, x86
Can access up to 4GB of external memory.
8KByte unified instruction and data cache
Parallel processing integral floating point unit,
Clock core speeds up to of 100 MHz in x1
Fully static design for dynamic clock control.
Low power and system management modes.
SDRAM Controller
64-bit data bus.
Up to 100MHz SDRAM clock speed.
Supports up to 128 MB system memory.
Supports 16-, 64- and 128-Mbit memories.
Supports up to 4 memory banks.
Supports buffered, non buffered, registered
4-line write buffers for CPU to DRAM and PCI
4-line read prefetch buffers for PCI masters.
Programmable latency
Programmable timing for DRAM parameters.
Supports -8, -10, -12, -13, -15 memory parts
Supports memory hole between 1MB and
PCI Controller
Compliant with PCI 2.1 specification.
Integrated PCI arbitration interface. Up to 3
Translation of PCI cycles to ISA bus.
Translation of ISA master initiated cycle to
Support for burst read/write from PCI master.
0.25X, 0.33X and 0.5X Host clock PCI clock.
ISA master/slave
Generates the ISA clock from either
Supports programmable extra wait state for
Supports I/O recovery time for back to back
Fast Gate A20 and Fast reset.
Supports the single ROM that C, D, or E.
processor fully PC compatible.
with write back and write through capability.
with automatic power down.
clock mode and 133MHz in x2 mode.
DIMMs
to DRAM cycles.
8MB for PCI/ISA busses.
masters can connect directly. External logic
allows for greater than 3 masters.
PCI.
14.318MHz oscillator clock or PCI clock
ISA cycles
I/O cycles.
blocks shares with F block BIOS ROM.
Release 1.3 - January 29, 2002
Supports flash ROM.
Supports ISA hidden refresh.
Buffered DMA & ISA master cycles to reduce
16-bit I/O decoding.
Local Bus interface
Multiplexed with ISA/DMA/Timer functions.
High speed, low latency bus.
Supports 32-bit Flash burst.
16-bit data bus with word steering capability.
Separate memory and I/O address spaces.
Programmable timing (Host clock granularity)
Supports 2 cachable banks of 16MB flash
2 Programmable Flash/EPROM Chip Select.
4 Programmable I/O Chip Select.
2-level hardware key protection for Flash boot
24 bit address bus.
EIDE Controller
Compatible with EIDE (ATA-2).
Backward compatibility with IDE (ATA-1).
Supports up to 4 IDE devices
Supports PIO and Bus Master IDE
Concurrent channel operation (PIO & DMA
Support for 11.1/16.6 MB/s, I/O Channel
Bus Master with scatter/gather capability.
Multi-word DMA support for fast IDE drives.
Individual drive timing for all four IDE devices.
Supports both legacy & native IDE modes.
Supports hard drives larger than 528MB.
Support for CD-ROM and tape peripherals.
Integrated Peripheral Controller
2X8237/AT compatible 7-channel DMA
2X8259/AT compatible interrupt Controller.
Three 8254 compatible Timer/Counters.
Co-processor error support logic.
Supports external RTC.
Power Management
Four power saving modes: On, Doze,
bandwidth utilization of the PCI and Host
bus. NSP compliant.
devices with boot block shadowed to
0x000F0000.
block protection.
modes) - 4 x 32-Bit Buffer FIFO per channel
Ready PIO data transfers.
controller.
16 interrupt inputs - ISA and PCI.
Standby, Suspend.