STPCI01 STMicroelectronics, STPCI01 Datasheet
STPCI01
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POWERFUL X86 PROCESSOR 64-BIT BUS ARCHITECTURE 64-BIT 66MHz DRAM CONTROLLER SVGA GRAPHICS CONTROLLER 135MHz RAMDAC UMA ARCHITECTURE TFT DISPLAY CONTROLLER PCI MASTER / SLAVE / ARBITER LOCAL BUS INTERFACE ISA (MASTER/SLAVE) INTERFACE -INCLUDING THE IPC PC-CARD INTERFACE - PCMCIA - ...
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STPC INDUSTRIAL X86 Processor core Fully static 32-bit 5-stage pipeline, x86 processor fully PC compatible. Access up to 4GB of external memory. 8Kbyte unified instruction and data cache with write back capability. Parallel processing integral floating point unit, with automatic ...
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ISA master/slave Generation of the ISA clock from either 14.318MHz oscillator clock or system clock Programmable extra wait state for ISA cycles Supports I/O recovery time for back to back I/O cycles. Fast Gate A20 and Fast reset. Supports the ...
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STPC INDUSTRIAL 4/69 Issue 2.4 - February 11, 2002 ...
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GENERAL DESCRIPTION At the heart of the STPC Industrial is an advanced 64-bit processor block, dubbed the 5ST86. The 5ST86 includes a powerful x86 processor core along with a 64-bit DRAM controller, advanced 64-bit accelerated graphics and video controller, ...
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GENERAL DESCRIPTION The need for system configuration jumpers is eliminated by providing address mapping support for PCMCIA 2.0 / JEIDA 4.1 PC-Card memory together with address windowing support for I/O space. Selectable interrupt steering from PC-Card to internal system bus ...
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Figure 1.1. Functionnal description. x86 Core Host I/F DRAM I/F Serial 2 ISA BUS Local ISA Bus I/F m/s PCI BUS PCI m/s CARDBUS HW Cursor GE VGA CRTC Issue 2.4 - February 11, 2002 GENERAL DESCRIPTION Serial 1 // ...
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GENERAL DESCRIPTION Figure 1.2. PCI, PCMCIA & CARDBUS modes: PCI m/s PCI m/s PCI m/s 8/69 PCI BUS PCMCIA CARDBUS PCI BUS PCMCIA CARDBUS PCI BUS PCMCIA CARDBUS Issue 2.4 - February 11, 2002 ...
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Figure 1.3. Local Bus and ISA bus modes: Local Bus I/F Local Bus I/F Figure 1.4. TFT in normal (serial 1 available) and extended modes (serial 1 unavailable). Kbd Serial 1 Mouse TFT I/F Serial 2 // Port ISA BUS ...
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GENERAL DESCRIPTION Figure 2. Typical PC oriented Application ISA MUX IRQ MUX DMA.REQ DMA.ACK DMUX PCI 10/69 Super I/O RTC Flash STPC Industrial 4x 16-bit EDO DRAMs Issue 2.4 - February 11, 2002 IDE Serial Ports Parallel Port Floppy Monitor ...
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Figure 3. Typical Embedded Application STPC Local Bus SRAM Flash PC-Card PCMCIA CARDBUS I/O Peripheral MUX IRQ STPC Industrial 4x 16-bit EDO DRAMs Issue 2.4 - February 11, 2002 GENERAL DESCRIPTION Monitor SVGA TFT Keyboard Mouse Serial Ports Parallel Port ...
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PIN DESCRIPTION 2 PIN DESCRIPTION 2.1. INTRODUCTION The STPC Industrial integrates most of the func- tionalities of the PC architecture. Therefore, many of the traditional interconnections between the host PC microprocessor and the peripheral devic- es are totally internal to ...
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Table 2-2. Definition of Signal Pins Signal Name Dir BASIC CLOCKS AND RESETS SYSRSTI#* SYSRSTO#* O XTALI XTALO O PCI_CLKI* PCI_CLKO O ISA_CLK, ISA_CLK2X O CLK14M O HCLK* I/O DEV_CLK* O GCLK2X I/O DCLK I/O V _xxx_PLL DD MEMORY INTERFACE ...
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PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir RMRTCCS#* O GPIOCS#* I/O IRQ_MUX[3:0]* DACK_ENC[2:0]* O DREQ_MUX[1:0]* TC* O KEYBOARD & MOUSE INTERFACE KBDATA*, MDATA* KBCLK*, MCLK* O SERIAL INTERFACE (SERIAL 1 COMBINED WITH TFT INTERFACE / SERIAL ...
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Table 2-2. Definition of Signal Pins Signal Name Dir CE1#*, CE2#* O VS1#*, VS2#* VCC5_EN* O VCC3_EN* O VPP_PGM* O VPP_VCC* O CARDBUS INTERFACE (COMBINED WITH PCI / PCMCIA) CCLKRUN* I/O CRST#* O CSTSCHG#* CAD[31:0]* I/O CBE[3:0]* I/O CFRAME#* I/O ...
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PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name Dir MONITOR INTERFACE RED, GREEN, BLUE O VSYNC* I/O HSYNC* I/O VREF_DAC RSET COMP DDC[1:0]* I/O SCL / DDC[1]* I/O SDA / DDC[0]* I/O TFT INTERFACE (COMBINED WITH SERIAL 1) ...
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SIGNAL DESCRIPTIONS 2.2.2 BASIC CLOCKS AND RESETS SYSRSTI# System Reset/Power good. This input is low when the reset switch is depressed. Other- wise, it reflects the power supply’s power good signal. PWGD is asynchronous to all clocks, and acts ...
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PIN DESCRIPTION CAS#[7:0] Column Address Strobe. There are 8 active low column address strobe outputs, one each for each Byte of the memory. The CAS# signals drive the SIMMs either directly or through external buffers. These pins are always outputs, ...
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MCS16# is always an input. The STPC Industrial ignores this signal during IO and refresh cycles. IOCS16# IO Chip Select16. This signal is the de- code of SA15-0 address pins ...
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PIN DESCRIPTION SOUT1, SOUT2 Serial Output. Data is clocked out using TCLK/16 (TCLK=BAUD#). DCD1#, DCD2# Input Data carrier detect. RI1#, RI2# Input Ring indicator. DSR1#, DSR2# Input Data set ready. CTS1#, CTS2# Input Clear to send. RTS1#, RTS2# Output Request ...
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Card therefore they will be forced low whenever a card is inserted in a socket. CE1#, CE2# Card Enable . These are active low output signals provided from the PCIC. CE#1 ena- bles even Bytes, CE#2 odd Bytes. ENABLE# Enable. ...
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PIN DESCRIPTION 2.2.13 MONITOR INTERFACE RED, GREEN, BLUE RGB Video Outputs. These are the three analog color outputs from the RAM- DACs. These signals are sensitive to interference, therefore they need to be properly shielded. VSYNC Vertical Synchronisation Pulse. This ...
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Table 2-3. Signals Sharing the Same Pin ISA BUS / IPC LOCAL BUS LA[23:22] FCS#[0], PRD#[1] LA[21:20] PA[21:20] LA[19:17] PRD#[0], PWR#[1:0] SA[19:1] PA[19:1] SA[0] PRDY# SD[15:0] PD[15:0] BHE# FCS#[1] MEMR#, MEMW# IOCS[3:2] SMEMR#, SMEMW# IOCS[1:0] GPIOCS# IOCHRDY IOR# IOW# MASTER# ...
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PIN DESCRIPTION PCI CARDBUS AD[19] CAD[19] AD[18] CAD[18] AD[17] CAD[17] AD[16] CAD[16] AD[15] CAD[15] AD[14] CAD[14] AD[13] CAD[13] AD[12] CAD[12] AD[11] CAD[11] AD[10] CAD[10] AD[9] CAD[9] AD[8:0] CAD[8:0] BE[3] CBE[3] BE[2] CBE[2] BE[1] CBE[1] BE[0] CBE[0] FRAME# CFRAME# TRDY# CTRDY# ...
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Table 2-4. Pinout. Pin # Pin Name C4 SYSRSTI# A3 SYSRSTO# AB25 XTALI AB23 XTALO G25 PCI_CLKI H23 PCI_CLKO B20 ISA_CLK A20 ISA_CLK2X AC26 CLK14M H26 HCLK J26 DEV_CLK AC15 GCLK2X AD16 DCLK AE13 MA[0] AC12 MA[1] AF13 MA[2] AD12 ...
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PIN DESCRIPTION Pin # Pin Name D3 SA[18] / PA[18] D2 SA[19] / PA[19] P2 SD[0] / PD[0] M3 SD[1] / PD[1] N1 SD[2] / PD[2] M4 SD[3] / PD[3] N2 SD[4] / PD[4] L3 SD[5] / PD[5] M1 SD[6] ...
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Pin # Pin Name B21 VPP_PGM A22 VPP_VCC AD4 RED AF4 GREEN AE5 BLUE AF3 VSYNC AE4 HSYNC AF5 VREF_DAC AE6 RSET AF6 COMP AE3 SDA / DDC[1] AF2 SCL / DDC[0] AE7 B[2] AF7 G[2] AD7 R[2] AE8 B[3] ...
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PIN DESCRIPTION 28/69 Issue 2.4 - February 11, 2002 ...
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STRAP OPTION This chapter defines the STPC Industrial Strap Options and their location. Memory Data Refer to Designation Lines MD16 PCI Clock PCI_CLKO Divisor MD17 MD18 Host Clock HCLK Pad Direction MD19 Graphics Clock GCLK2x Pad Direction MD20 DOT ...
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STRAP OPTION 3.1. STRAP OPTION REGISTER DESCRIPTION 3.1.1. STRAP REGISTER 0 This register reflect the status of pins MD[7:0] respectively. They are expected to be connected on the system board to the SIMM configuration pins as follows: Strap0 7 6 ...
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STRAP REGISTER 1 This register reflect the status of pins MD[15:8] respectively. They are expected to be connected on the system board to the SIMM configuration pins as follows: Strap1 7 6 MD15 MD14 This register defaults to the ...
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STRAP OPTION 3.1.3. STRAP REGISTER 2 Bits 4-0 of this register reflect the status of pins MD[20:16] respectively. Bit 5 of this register reflect the sta- tus of pin MD[23]. Bit 4 is writeable, writes to other bits in this ...
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STRAP REGISTER 3 Bits 7-0 of this register reflect the status of pins MD[47:40] respectively. Strap3 7 6 Rsv This register defaults to the values sampled on MD[47:40] pins after reset Bit Number Sampled Mnemonic Bits 7-6 Rsv Bit ...
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STRAP OPTION 3.1.5. STRAP REGISTER 4 Bits 5-0 of this register reflect the status of pins MD[53:48] respectively. Strap4 7 6 Rsv This register defaults to the values sampled on MD[53:48] pins after reset Bit Number Sampled Mnemonic Bits 7-5 ...
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HCLK PLL STRAP REGISTER 0 Bits 5-0 of this register reflect the status of pins MD[26:21] respectively. HCLK_Strap0 7 6 Rsv This register defaults to the values sampled on pins described below after reset Bit Number Sampled Mnemonic Bits ...
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STRAP OPTION 36/69 Issue 2.4 - February 11, 2002 ...
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ELECTRICAL SPECIFICATIONS 4.1 INTRODUCTION The electrical specifications in this chapter are valid for the STPC Industrial. 4.2 ELECTRICAL CONNECTIONS 4.2.1 Power/Ground Connections/Decoupling Due to the high frequency of operation of the STPC Industrial necessary to install and ...
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ELECTRICAL SPECIFICATIONS 4.3.1 5V Tolerance The STPC is capable of running with I/O systems that operate at 5V such as PCI and ISA devices. Certain pins of the STPC tolerate inputs up to 4.4 DC CHARACTERISTICS Table 4-2. DC Characteristics ...
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AC CHARACTERISTICS Table 4-5 through Table 4-22 characteristics including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 4-1. The rising clock edge reference level ...
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ELECTRICAL SPECIFICATIONS 4.5.1 POWER ON SEQUENCE 3.3V Supply 14M TI# Strap O ptions I_C SYSRSTI# has no constraint ...
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PCI AC Timing characteristics Table 4-5. PCI Bus AC Timing Name Parameter t1 PCI_CLKI to AD[31:0] valid t2 PCI_CLKI to FRAME# valid t3 PCI_CLKI to CBE#[3:0] valid t4 PCI_CLKI to PAR valid t5 PCI_CLKI to TRDY# valid t6 PCI_CLKI ...
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ELECTRICAL SPECIFICATIONS Figure 4-3 Memory Early Write Mode (ref table tCMA CLK tCRP RAS# CAS# MA MWE# MD Figure 4-4 EDO Read Mode (ref table tCMA CLK tRP tRP tCRP RAS# CAS# MA MWE# MD 42/69 Table 4-6) tCRAS tCCAS ...
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Figure 4-5 Fast Page Mode Read (ref table tCRAS tCMA tCCAS CLK tCRP tRAH tRAD tAR tCSH tRCD RAS# tCAH tCPN tCPN tCOH CAS# MA ROW Column 1 MWE# MD Figure 4-6 Fast Page Mode Write (ref table tCRAS tCMD ...
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ELECTRICAL SPECIFICATIONS Figure 4-7 Refresh Cycle (ref table CLK MA[11:0] tRP tRP tRPC RAS#[3:0] tCPN tCPN CAS#[7:0] Table 4-6. AC Memory Timing Characteristics Parameter tCRAS HCLK (or GCLK2X) to RAS#[3:0] valid (see Note 3) tCCAS HCLK (or GCLK2X) to CAS#[7:0] ...
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Table 4-6. AC Memory Timing Characteristics Parameter tRCH Read Command Hold Time tRCS Read Command Setup Time tRP RAS Precharge Time tWCH Write Command Hold Time tWCS WE Command Setup Time tWRH WE Hold Time tWRP WE Setup Time tAR ...
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ELECTRICAL SPECIFICATIONS 4.5.4 ISA INTERFACE AC TIMING CHARACTERISTICS Figure 4-8 ISA Cycle (ref table 2 ALE AEN Valid AENx 3 LA [23:17] Valid Address SA [19:0] CONTROL (Note 1) IOCS16# MCS16# IOCHRDY READ DATA WRITE DATA Note 1; Stands for ...
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Table 4-8. ISA Bus AC Timing Name Parameter 11a Memory access to 16 bit ISA Slave - 2BCLK 11b Memory access to 16 bit ISA Slave - Standard 3BCLK 11c Memory access to 16 bit ISA Slave - 4BCLK 11d ...
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ELECTRICAL SPECIFICATIONS Table 4-8. ISA Bus AC Timing Name Parameter 25 MEMR#, MEMW# asserted before next ALE# asserted 25b Memory access to 16 bit ISA Slave Standard cycle 25d Memory access to 8 bit ISA Slave Standard cycle 25 SMEMR#, ...
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Table 4-8. ISA Bus AC Timing Name Parameter 41c I/O access to 16 bit ISA Slave 41d I/O access to 8 bit ISA Slave 42 SA[19:0] SBHE valid to read data valid 42b Memory access to 16 bit ISA Slave ...
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ELECTRICAL SPECIFICATIONS Table 4-8. ISA Bus AC Timing Name Parameter MEMW# negated to copy data float, 8 bit ISA Slave, odd Byte 64f by ISA Master IOW# negated to copy data float, 8 bit ISA Slave, odd Byte by 64g ...
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KEYBOARD INTERFACE AC TIMING CHARACTERISTICS Table 4-12. Keyboard Interface AC Timing Name Parameters t40 Input setup to KBCLK t41 Input hold to KBCLK t42 KBCLK to KBDATA 4.5.9 MOUSE INTERFACE AC TIMING CHARACTERISTICS Table 4-13. Mouse Interface AC Timing ...
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ELECTRICAL SPECIFICATIONS 4.5.10 LOCAL BUS INTERFACE AC TIMING CHARACTERISTICS Table 4-14. 16 bit Memory Write t58 HCLK PA PD IOCS#[3:0] PWR#0 PWR#1 PRD#0 PRD#1 Table 4-15. 16 bit Memory Read t58 HCLK PA PD IOCS#[3:0] PWR#0 PWR#1 PRD#0 PRD#1 Table ...
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Table 4-17. 16 bit I/O Read t58 HCLK PA PD IOCS#[3:0] PWR#0 PWR#1 PRD#0 PRD#1 Table 4-18. 8 bit I/O Write at even addresses with IOWIDTH t58 HCLK PA PD[7:0] PD[15:8] IOCS#[3:0] PWR#0 PWR#1 PRD#0 PRD#1 Table 4-19. ...
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ELECTRICAL SPECIFICATIONS Table 4-20. 8 bit I/O Write at odd addresses with IOWIDTH=1 (16 bit Peripheral) t58 HCLK PA PD[7:0] PD[15:8] IOCS#[3:0] PWR#0 PWR#1 PRD#0 PRD#1 Table 4-21. Local Bus Interface AC Timing Name Parameters t46 PRDY# Input hold to ...
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Table 4-22. TFT Interface Timing Name Parameters t70 DCLK to B[5] t71 DCLK to FPFRAME ELECTRICAL SPECIFICATIONS Issue 2.4 - February 11, 2002 Min Max Units 55/69 ...
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ELECTRICAL SPECIFICATIONS 56/69 Issue 2.4 - February 11, 2002 ...
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MECHANICAL DATA 5.1. 388-PIN PACKAGE DIMENSION The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure Figure 5-1. 388-Pin PBGA Package - Top View ...
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MECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols Min A 34.95 B 1.22 C 0.58 D 1.57 E 0.15 F 0.05 G 0.75 58/69 ...
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Figure 5-3. 388-pin PBGA Package - Dimensions C Solderball A Table 5-2. 388-pin PBGA Package - Dimensions Symbols Min A 0.50 B 1.12 C 0.60 D 0.52 E 0. Solderball after collapse G mm Typ ...
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MECHANICAL DATA 5.2. 388-PIN PACKAGE THERMAL DATA The 388-pin PBGA package has a Power Dissipation Capability of 4.5W. This increases to 6W when used with a Heatsink. Signal layers Figure 5-5. Thermal Dissipation Without Heatsink Board Ambient Rca Case Rjc ...
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Figure 5-6. Thermal Dissipation With Heatsink Board Ambient Rca Case Rjc Board Junction 8.5 Rjb Board Rba Ambient Rja = 9.5 °C/W Board dimensions: Junction - 10 12 layers (2 for signals, 1 GND, 1VCC) ...
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MECHANICAL DATA 5.3. SOLDERING RECOMMENDATIONS High quality, low defect soldering requires identifying the optimum temperature profile for reflowing the solder paste, therefore optimizing the process. The heating and cooling rise rates must be compatible with the solder paste and components. ...
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BOARD LAYOUT 6.1. THERMAL DISSIPATION Thermal dissipation of the STPC depends mainly on supply voltage. When the system does not need to work at 3 may be beneficial to reduce the voltage to, for example, 3.15 V. ...
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BOARD LAYOUT When considering thermal dissipation, the most important - if not the most obvious - part of the layout is the connection between the ground balls and the ground layer. A 1-wire connection is shown in use of 8-mil ...
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Figure 6-4. Optimum Layout for Central Ground Ball The PBGA Package also dissipates heat through the peripheral ground balls. When a heat sink is placed on the device, heat is more uniformly spread throughout the moulding, increasing the dissipation of ...
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BOARD LAYOUT Figure 6-1. Global Ground Layout for Good Thermal Dissipation Figure 6-2. Bottom Side Layout and Decoupling 66/69 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. ...
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Figure 6-3. Use of Metal Plate for Thermal Dissipation Metal planes This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Die Issue 2.4 - February 11, 2002 BOARD ...
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BOARD LAYOUT 6.2. HIGH SPEED SIGNALS As some STPC interfaces (listed below in decreasing speed order) run at high speeds, they must be carefully routed or even shielded. 1) Memory interface. 2) Graphics and video interfaces. 3) PCI bus. ground ...
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... ORDERING DATA 7.1 ORDERING CODES STMicroelectronics Prefix Product Family PC: PC Compatible Product ID I01: Industrial Core Speed 66: 66MHz 80: 80MHz Package BT: 388 Overmoulded BGA Temperature Range C: Commercial Tcase = 0 to +100°C I: Industrial Tcase = -40 to +100°C Operating Voltage 3 : 3.3V ± 0. I01 Issue 2.4 - February 11, 2002 ...
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... ORDERING DATA 7.2 AVAILABLE PART NUMBERS Core Frequency Part Number STPCI0166BTC3 STPCI0180BTC3 STPCI0166BTI3 STPCI0180BTI3 70/69 CPU Mode (MHz Issue 2.4 - February 11, 2002 Tcase Range Operating Voltage (C) 0°C to +100°C 3.3V ± 0.3V -40°C to +100°C (V) ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...