STPC STMicroelectronics, STPC Datasheet
STPC
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STPC Summary of contents
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... The chip also in- cludes a built-in digital TV encoder and anti-flicker filters that allow stable, high-quality display on standard PAL or NTSC television sets without ad- ditional components. The STPC Consumer is packaged in a 388 Plastic Ball Grid Array (PBGA). 8/2/00 STPC CONSUMER PC Compatible Embeded Microprocessor Figure 1 ...
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... DRAM speeds. Memory hole between 1 MByte & 8 MByte supported for PCI/ISA busses. Hidden refresh. To check if your memory device is supported by the STPC, please refer to Table 9-3 in the Programming Manual. Graphics Engine 64-bit windows accelerator. Backward compatibility to SVGA standards. Hardware acceleration for text, bitblts, transparent blts and fills ...
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... IDE Interface Supports PIO Supports up to Mode 5 Timings Transfer Rates to 22 MBytes/sec Supports IDE devices STPC CONSUMER Concurrent channel operation (PIO modes 32-Bit Buffer FIFOs per channel Support for PIO mode 3 & 4. Support for 11.1/16.6 MB/s, I/O Channel Ready PIO data transfers. ...
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... STPC CONSUMER www.DataSheet4U.com 4/51 Issue 1.2 ...
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... UPDATE HISTORY FOR OVERVIEW. The following changes have been made to the Electrical Specification Chapter on the 02/02/2000. Section Change Added www.DataSheet4U.com UPDATE HISTORY FOR OVERVIEW. Text To check if your memory device is supported by the STPC, please refer to Table 9-3 Host Address to MA Bus Mappingin the Programming Manual. Issue 1.2 5/51 ...
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... GENERAL DESCRIPTION 1. GENERAL DESCRIPTION At the heart of the STPC Consumer is an ad- vanced processor block, dubbed the 5ST86. The 5ST86 includes a powerful x86 processor core along with a 64-bit DRAM controller, advanced 64bit accelerated graphics and video controller, a high speed PCI local-bus controller and Industry ...
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... The STPC Consumer has been designed using modern reusable modular design techniques possible to add or remove the standard features of the STPC Consumer or other variants of the 5ST86 family. Contact your local STMicroelecton- ics sales office for further information. Issue 1.2 ...
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GENERAL DESCRIPTION Figure 1-1 Functionnal description x86 Core Host I/F www.DataSheet4U.com DRAM 8/51 ISA PCI m/s PCI m/s VIP Video Color pipeline Key 2D Chroma SVGA CRTC HW Cursor Issue 1.2 ISA BUS IPC EIDE EIDE PCI BUS CCIR Input ...
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... Figure 1-2 Typical Application www.DataSheet4U.com ISA MUX MUX DMUX PCI Super I/O RTC Flash IRQ DMA.REQ STPC Consumer DMA.ACK 4x 16-bit EDO DRAMs Issue 1.2 GENERAL DESCRIPTION Keyboard / Mouse Serial Ports Parallel Port Floppy 2x EIDE DMUX Monitor SVGA TV S-VHS RGB PAL NTSC Video CCIR601 CCIR656 ...
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... PC architecture result, many of the traditional interconnections between the host PC microprocessor and the peripheral devic- es are totally internal to the STPC Consumer. This offers improved performance due to the tight cou- pling of the processor core and these peripherals result many of the external pin connections www ...
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Table 2-2. Definition of Signal Pins Signal Name BASIC CLOCKS AND RESETS SYSRSTI# XTALI XTALO HCLK DEV_CLK GCLK2X DCLK www.DataSheet4U.com PCI_CLKI PCI_CLKO SYSRSTO# ISA_CLK ISA_CLK2X MEMORY INTERFACE MA[11:0] RAS#[3:0] CAS#[7:0] MWE# MD[63:0] PCI INTERFACE AD[31:0] CBE[3:0] FRAME# TRDY# IRDY# STOP# ...
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PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name ISA/IDE COMBINED CONTROL IOCHRDY / DIORDY ISA CONTROL OSC14M ALE BHE# www.DataSheet4U.com MEMR#, MEMW# SMEMR#, SMEMW# IOR#, IOW# MASTER# MCS16#, IOCS16# REF# AEN ZWS# IOCHCK# ISAOE# RTCAS# GPIOCS# IDE CONTROL ...
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Table 2-2. Definition of Signal Pins Signal Name SDA / DDC[0] COL_CMP VIDEO INPUT VCLK VIN DIGITAL TV OUTPUT www.DataSheet4U.com RED_TV, GREEN_TV, BLUE_TV VCS ODD_EVEN CVBS IREF1_TV VREF1_TV IREF2_TV VREF2_TV VSSA_TV VDDA_TV MISCELLANEOUS SPKRD SCAN_ENABLE Dir Description I ...
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... Balance capacitors should also be added. In the event of an external oscillator providing the master clock signal to the STPC Consumer device, the TTL signal should be provided on XTALO. HCLK Host Clock. This is the host 1X clock. Its frequency can vary from MHz. All host transactions and PCI transactions are synchro- nized to this clock ...
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MD[63:0] Memory Data I/O. This is the 64-bit memory data bus. If only half of a bank is populat- ed, MD63-32 is pulled high, data is on MD31-0. MD[40-0] are read by the device strap option reg- isters during rising ...
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... SERR# System Error. This is the system error sig- nal of the PCI bus. It may, if enabled, be asserted for one PCI clock cycle if target aborts a STPC Consumer initiated PCI transaction. Its assertion by either the STPC Consumer or by another PCI bus agent will trigger the assertion of NMI to the host CPU ...
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LA[22]/SCS1# Unlatched Address (ISA)/Second- ary Chip Select (IDE) This pin has two functions, depending on whether the ISA bus is active or the IDE bus is active. When the ISA bus is active, this pins is ISA Bus unlatched address ...
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... The STPC Consumer does not drive IOCS16# (similar to PC-AT design). An ISA mas- ter access to an internal register of the STPC Con- sumer is executed as an extended 8-bit IO cycle. REF# Refresh Cycle. This is the refresh command signal of the ISA bus driven as an output when the STPC Consumer performs a refresh cy- cle on the ISA bus ...
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... Active low output. 2.2.10 IPC IRQ_MUX[3:0] Multiplexed Interrupt Request. These are the ISA bus interrupt signals. They are to be encoded before connection to the STPC Consumer using ISACLK and ISACLKX2 as the input selection strobes. Note that IRQ8B, which by convention is connect the RTC, is inverted before being sent to the interrupt controller, so that it may be connected di- rectly to the IRQ pin of the RTC ...
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PIN DESCRIPTION ed to ISAOE# and the output is provided with a weak pull-up resistor. RTCRW# / DD[13] Real Time Clock RW. This pin is a multi-function pin. When ISAOE# is active, this signal is used as RTCRW#. This signal ...
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Table 2-3. Pinout. Pin # Pin name AF3 SYSRSTI A3 XTALI C4 XTALO G23 HCLK F25 DEV_CLK AF15 GCLK2X AF9 DCLK AD15 MA[0] www.DataSheet4U.com AF16 MA[1] AC15 MA[2] AE17 MA[3] AD16 MA[4] AF17 MA[5] AC17 MA[6] AE18 MA[7] AD17 MA[8] ...
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PIN DESCRIPTION Pin # Pin name B21 PCI_GNT#[1] D20 PCI_GNT#[2] A5 PCI_INT[0] C6 PCI_INT[1] B4 PCI_INT[2] D5 PCI_INT[3] F2 LA[17]/DA[0] G4 LA[18]/DA[1] F3 LA[19]/DA[2] www.DataSheet4U.com F1 LA[20]/PCS1# G2 LA[21]/PCS3# G3 LA[22]/SCS1# H2 LA[23]/SCS3# J4 SA[0] H1 SA[1] H3 SA[2] J2 ...
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Pin # Pin name D18 VDD5 A22 VDD B14 VDD C9 VDD D6 VDD D11 VDD D16 VDD D21 VDD F4 VDD F23 VDD www.DataSheet4U.com G1 VDD K23 VDD L4 VDD L23 VDD P2 VDD T4 VDD T23 VDD T26 ...
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PIN DESCRIPTION www.DataSheet4U.com 24/51 Issue 1.2 ...
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Update History for Pin Description chapter The following changes have been made to the Pin Description Chapter on 08/02/2000 Section Change Added 2.2 The following changes have been made to the Pin Description Chapter on 13/01/2000 www.DataSheet4U.com Section Change ...
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Update History for Pin Description chapter www.DataSheet4U.com 26/51 Issue 1.2 ...
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... STRAP OPTION This chapter defines the STPC Consumer Strap Options and their location Memory Data Note Refer to Lines MD0 1 MD1 MD2 2 DRAM Bank 1 www.DataSheet4U.com MD3 2 MD4 2 MD5 2 DRAM Bank 0 MD6 2 MD7 2 MD8 2 MD9 2 MD10 2 DRAM Bank 3 MD11 2 MD12 2 MD13 2 DRAM Bank 2 ...
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STRAP OPTION Memory Data Note Refer to Lines MD38 MD39 MD40 MD41 MD42 MD43 Note; www.DataSheet4U.com 1) This Strap Option selects between two different functional blocks, the first is the ISA (SMEMW#) and the other is the VGA block (Color_Key). ...
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Bit 1 This bit reflects the value sampled on MD[17] pin and controls the PCI clock output as follows: 0: PCI clock output = HCLK / 2 1: PCI clock output = HCLK / 3 Bit 0; Reserved This register ...
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... Electrical Connections 4.2.1 Power/Ground Connections/Decoupling www.DataSheet4U.com Due to the high frequency of operation of the STPC Consumer necessary to install and test this device using standard high frequency tech- niques. The high clock frequencies used in the STPC Consumer and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously ...
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... VREF , and other reference levels are shown in Table 4-3 below for the STPC Consumer. Input or output signals must cross these levels during testing. Figure 4-1 shows output delay (A and B) and input setup and hold times (C and D). Input setup and ...
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ELECTRICAL SPECIFICATIONS Figure 4-1 Drive Level and Measurement Points for Switching Characteristics CLK: www.DataSheet4U.com OUTPUTS: INPUTS: LEGEND Maximum Output Delay Specification B - Minimum Output Delay Specification C - Minimum Input Setup Specification D - Minimum Input Hold ...
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AC Timing parameters Table 4-4. PCI Bus AC Timing Name Parameter t1 PCI_CLKI to AD[31:0] valid t2 PCI_CLKI to FRAME# valid t3 PCI_CLKI to CBE#[3:0] valid t4 PCI_CLKI to PAR valid t5 PCI_CLKI to TRDY# valid www.DataSheet4U.com T6 PCI_CLKI ...
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ELECTRICAL SPECIFICATIONS Table 4-7. Video Input AC Timing Name Parameter t35 VIN[7:0] setup to VCLK t36 VIN[7:0] hold from VCLK t37 VCLK to ODD_EVEN valid t38 VCLK to VCS valid t39 ODD_EVEN setup to VCLK t40 ODD_EVEN hold from VCLK ...
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Update History for Electrical Specification chapter The following changes have been made to the Electrical Specification Chapter on the 07/02/2000. Section Change 4.5 Revued The following changes have been made to the Electrical Specification Chapter on the 20/10/99. www.DataSheet4U.com ...
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Update History for Electrical Specification chapter www.DataSheet4U.com 36/51 ...
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... MECHANICAL DATA 5.1 388-Pin Package Dimension The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure 5-1. Figure 5-1. 388-Pin PBGA Package - Top View ...
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MECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner www.DataSheet4U.com A Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols A 34. 38/ Detail C G ...
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Figure 5-3. 388-pin PBGA Package - Dimensions www.DataSheet4U.com Table 5-2. 388-pin PBGA Package - Dimensions Symbols Solderball Solderball after collapse Min Typ Max 0.50 0.56 0.62 1.12 1.17 1.22 ...
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MECHANICAL DATA 5.2 388-Pin Package thermal data 388-pin PBGA package has a Power Dissipation Capability of 4.5W which increases to 6W when used with a Heatsink. Figure 5-4. 388-Pin PBGA structure Signal layers www.DataSheet4U.com Figure 5-5. Thermal dissipation without heatsink ...
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Figure 5-6. Thermal dissipation with heatsink www.DataSheet4U.com Board Ambient Case Junction Board Ambient Junction Rca 3 6 Rjc Board Case 8.5 50 Rjb Ambient Rba Rja = 9.5 C/W Issue 1.2 MECHANICAL DATA Board dimensions 12.7 ...
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MECHANICAL DATA www.DataSheet4U.com 42/51 Issue 1.2 ...
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... Add- ing a heat sink reduces this value to 85 result, some basic rules have to be applied when routing the STPC in order to avoid thermal problems. First of all, the whole ground layer acts as a heat sink and ground balls must be directly connected illustrated in Figure 6-1 ...
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BOARD LAYOUT When considering thermal dissipation, the most important - and not the more obvious - part of the layout is the connection between the ground balls and the ground layer. A 1-wire connection is shown in Figure 6-2. The ...
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Figure 6-4. Optimum layout for central ground ball www.DataSheet4U.com The PBGA Package also dissipates heat through peripheral ground balls. When a heat sink is placed on the device, heat is more uniformely spread throughout the moulding increasing heat dissipation through ...
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BOARD LAYOUT Figure 6-6. Bottom side layout and decoupling www.DataSheet4U.com A local ground plane on opposite side of the board as shown in Figure 6-6 improves thermal dissipa- tion used to connect decoupling capacitances but can also be ...
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... HIGH SPEED SIGNALS Some Interfaces of the STPC run at high speed and have to be carefully routed or even shielded. Here is the list of these interfaces, in decreasing speed order: - Memory Interface. - Graphics and video interfaces www.DataSheet4U.com - PCI bus - 14MHz oscillator stage Figure 6-8. Shielding signals All the clocks have to be routed first and shielded for speeds of 27MHz or more ...
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... ORDERING DATA 7. ORDERING DATA 7.1 Ordering Codes STMicroelectronics Prefix www.DataSheet4U.com Product Family PC: PC Compatible Product ID C01: Consumer Core Speed 66: 66MHz 75: 75MHz 80: 80MHz 10: 100MHz Package BT: 388 Overmoulded BGA Temperature Range C: Commercial 0 to +70 C Tcase = 0 to +100 C I: Industrial -40 to +85 C Tcase = -40 to +100 C Operating Voltage ...
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... Available Part Numbers Part Number STPCC0166BTC3 STPCC0180BTC3 STPCC0110BTC3 STPCC0166BTI3 STPCC0180BTI3 www.DataSheet4U.com Core Frequency CPU Mode (MHz 100 DX2 +100 Issue 1.2 ORDERING DATA Tcase Range Operating Voltage (C) ( +100 C 3.3V 0.3V 49/51 ...
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ORDERING DATA www.DataSheet4U.com 50/51 Issue 1.2 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics ...