SC2200UFH-300F 33 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300F 33 Datasheet - Page 170

• Manufacturer Part Number: SC2200UFH-300F 33
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300F 33

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.2.12.2 AC97 Codec Interface
The AC97 codec is the master of the serial interface and
generates the clocks to Core Logic module. Figure 6-13
shows the signal connections between two codecs and the
SC2200:
• Codec1 can be AC97 Rev. 1.3 or higher compliant.
• Codec2 is optional, but must be compliant with AC97 2.0
• For PC speaker synthesis, the Core Logic module
178
or higher. (For specifics on the serial interface, refer to
the appropriate codec manufacturer’s data book.):
— SDATA_IN2 has wakeup capability. (See Section 5.6
— If SDATA_IN2 is not used it must be connected to
— If an AMC97 codec is used (as Codec2), it should be
outputs the PC speaker signal on the PC_BEEP pin
which is connected to the PC_BEEP input of the AC97
codec. Note that PC_BEEP is muxed with GPIO16 and
must be programmed via PMR[0] (see Table 4-2 on
page 76.)
"System Wakeup Control (SWC)" on page 123.)
V
connected to SDATA_IN2 and SDATA_IN should be
connected to V
SS
.
AMD Geode™
SC2200
Processor
SS
SDATA_OUT
32580B
.
SDATA_IN2
SDATA_IN
AC97_CLK
PC_BEEP
BIT_CLK
SYNC
Figure 6-13. AC97 V2.0 Codec Signal Connections
Codec Configuration/Control Registers
The codec 32-bit related registers:
• GPIO Status and Control Registers:
• Codec Status Register (F3BAR0+Memory Offset 08h)
• Codec Command Register (F3BAR0+Memory Offset
Codec GPIO Status and Control Registers:
The Codec GPIO Status and Control registers are used for
codec GPIO related tasks such as enabling a codec GPIO
interrupt to cause an SMI.
Codec Status Register:
The Codec Status register stores the codec status WORD.
It is updated every valid Status Word slot.
Codec Command Register:
The Codec Command register writes the control WORD to
the codec. By writing the appropriate control WORDs to
this port, the features of the codec can be controlled. The
contents of this register are written to the codec during the
Control Word slot.
The bit formats for these registers are given in Table 6-38
"F3BAR0+Memory Offset: Audio Configuration Registers"
on page 273.
— Codec GPIO Status Register (F3BAR0+Memory
— Codec GPIO Control Register (F3BAR0+Memory
0Ch)
Offset 00h)
Offset 04h)
BIT_CLK
XTAL_I
SYNC
PC_BEEP
SDATA_OUT
SDATA_IN
BIT_CLK
XTAL_I
SYNC
PC_BEEP
SDATA_OUT
SDATA_IN2
AMD Geode™ SC2200 Processor Data Book
(Optional)
Codec2
Codec1
Core Logic Module