SC2200UFH-300F 33 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300F 33 Datasheet - Page 419

• Manufacturer Part Number: SC2200UFH-300F 33
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300F 33

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Electrical Specifications
ACPI is non-functional and all ACPI outputs are undefined when the power-up sequence does not include using the power
button. SUSP# is an internal signal generated from the ACPI block. Without an ACPI reset, SUSP# can be permanently
asserted. If the USE_SUSP bit in CCR2 of GX1 module is enabled (Index C2h[7] = 1), the CPU will stop.
If ACPI functionality is desired, or the situation described above avoided, the power button must be toggled. This can be
done externally or internally. GPIO63 is internally connected to PWRBTN#. To toggle the power button with software,
GPIO63 must be programmed as an output using the normal GPIO programming protocol (see Section 6.4.1.1 "GPIO Sup-
port Registers" on page 233). GPIO63 must be pulsed low for at least 16 ms and not more than 4 sec.
Asserting POR# has no effect on ACPI. If POR# is asserted and ACPI was active prior to POR#, then ACPI will remain
active after POR#. Therefore, BIOS must ensure that ACPI is inactive before GPIO63 is pulsed low.
AMD Geode™ SC2200 Processor Data Book
Symbol
t
t
t
1
2
3
1)
2)
V
SBL,
V
V
V
SBL
SB
V
SB,
32KHZ
CORE
POR#
and V
Table 9-45. Power-Up Sequence Not Using the Power Button Timing Parameters
and V
V
Parameter
Voltage sequence
POR# inactive after V
and V
32KHZ startup time
IO
1
2
IO
Figure 9-56. Power-Up Sequencing Without PWRBTN# Timing Diagram
CORE
IO
should be tied together.
applied
should be tied together.
t
1
SBL
, V
t
2
CORE
, V
SB
,
-100
Min
50
t
3
Max
100
1
Unit
ms
ms
s
Comments
Optimum power-up results with
t
POR# must not glitch during
active time.
Time required for 32 KHz oscilla-
tor and 14.318 MHz derived from
PLL6 to become stable at which
time the RTC can reliably count.
Spec assumes unbalanced exter-
nal circuit. See Section 5.5.2.1 on
page 111 for more details.
1
= 0.
32580B
437