PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 175

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
11.6.4
The BIU_Status register holds bits that track the status of
bus cycles initiated by the DSPCPU and bus cycles from
external devices that write into SDRAM.Two bits of sta-
tus are provided for each type of bus cycle: a busy bit and
a done bit. The DSPCPU can read both bits; a done bit
is cleared by writing a ‘1’ to it. The status register also
holds two error-flag bits.
DSPCPU software must check the busy bits to avoid is-
suing a PCI interface bus cycle request while a request
of a similar type is in progress. If a bus cycle is issued
while a request of similar type is in progress, the PCI in-
terface ignores the second command and sets the ap-
propriate error bit in the status register.
When the DSPCPU issues either an io_cycle or
config_cycle request while a previous request of either
type is already in progress, the PCI interface sets bit 8 in
BIU_STATUS. When the DSPCPU issues a dma_cycle
while a previous one is already in progress, the PCI inter-
face sets bit 9 in BIU_STATUS. To reset either of the er-
ror bits 8 or 9 in BIU_STATUS write a ‘1’ to it.
RTA (Received target abort). This bit is set when
PNX1300 initiated a transaction that was aborted by the
target. To reset this bit, write a ‘1’ to this bit position. This
bit is set simultaneous with the RTA bit in the configura-
tion space status register, but is cleared independently.
RMA (Received master abort). This bit is set when
PNX1300 initiated a transaction and aborts it. This usu-
ally signals a transaction to a nonexistent device. To re-
set this bit, write a ‘1’ to this bit position. This bit is set si-
multaneous with the RMA bit in the configuration space
status register, but is cleared independently.
TTE (Target timer expired). In normal operation, a read
of a PNX1300 data item is performed on retry basis:
PNX1300 tells the external master to retry, meanwhile it
fetches the data item across the highway. This bit is set
if an external master did not retry a read of a PNX1300
data item within 32768 PCI clocks. The requested data is
discarded. To reset this bit, write a ‘1’ to this bit position.
This is purely a software information bit. No software ac-
tion is required when this condition occurs, but it may in-
dicate a non-compliant or defective master on the bus.
11.6.5
The BIU_CTL register contains bits that control miscella-
neous aspects of the PCI interface operation. Following
are descriptions of the fields.
Table 11-12. PCI MMIO registers and bus cycles
mmio_cycle
(MMIO register R/W)
mem_cycle
(PCI-space memory R/W)
dma_cycle
(Block data transfer)
Internal Cycle
BIU_STATUS Register
BIU_CTL Register
All registers accessible by
external PCI devices
PCI_ADR,
PCI_DATA
SRC_ADR,
DEST_ADR,
DMA_CTL
Registers Involved
Table 11-12. PCI MMIO registers and bus cycles
Table 11-13. PCI MMIO register accessibility
SE (Swap bytes enable). This bit is initialized after reset
to ’0’, which causes the PCI interface to operate in its de-
fault big-endian mode. Writing a ’1’ to SE causes access-
es to MMIO registers over the PCI interface to be made
in little endian mode.
BO (Burst mode off). This bit is initialized to ’0’, which
allows the PCI interface to support burst-mode writes as
a target on the PCI bus. Setting this bit to ’1’ disables
burst-mode writes.
With burst mode enabled, the PCI interface buffers as
much data as possible into r_buffer before issuing a dis-
connect to the PCI initiator. With burst mode disabled,
the PCI interface buffers only one data phase before is-
suing a disconnect to the PCI initiator.
IntE (Interrupt enables). The bits in the IntE field control
the signaling of interrupts to the DSPCPU for PCI inter-
face events. These events raise DSPCPU interrupt 16 if
enabled. Interrupt 16 must be set up as a level triggered
interrupt.
IntE is initially set to ‘0’s (interrupts disabled).
Note that the error condition masked by bit 6 (see
tion 11.6.4, “BIU_STATUS
a config_cycle or an io_cycle is requested and a request
of either type is already in progress. That is, the second
PRELIMINARY SPECIFICATION
IO_cycle
(I/O register R/W)
config_cycle
(Configuration register R/W)
DRAM_BASE
MMIO_BASE
BIU_STATUS
BIU_CTL
PCI_ADR
PCI_DATA
CONFIG_ADR
CONFIG_DATA
CONFIG_CTL
IO_ADR
IO_DATA
IO_CTL
SRC_ADR
DEST_ADR
DMA_CTL
INT_CTL
Register
Internal Cycle
Table 11-14
MMIO_BASE
0x10 300C
0x10 301C
0x10 302C
0x10 0000
0x10 0400
0x10 3004
0x10 3008
0x10 3010
0x10 3014
0x10 3018
0x10 3020
0x10 3028
0x10 3030
0x10 3034
0x10 3038
0x10 3024
Offset
lists the function of each IntE bit.
Register”) occurs when either
IO_ADR,
IO_DATA,
IO_CTL
CONFIG_ADR,
CONFIG_DATA,
CONFIG_CTL
Registers Involved
DSPCPU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Accessibility
PCI Interface
External
Initiator
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–/–
–/–
11-11
Sec-