PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 280

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
Where
As an example, if CPU
is 3 and L3
• D
• D
If CPU/SDRAM ratio is 5/4 (for example memory fre-
quency is 80 MHz and CPU frequency is 100 MHz), re-
fresh interval K
maximum latency for VO is:
• L
• L
Note: Average latency is normally much lower than worst
case latency because on rare occasions many units will
issue requests at exactly the same time (this is assumed
when evaluating the maximum latency).
Note: All real-time units have a special exception notifi-
cation flag that is raised if an overflow or underflow oc-
curs while operating.
Note: To compute the latency L
abled, its weight has to be set to ‘0’ in the D
equations and in D
These equations are not accurate for all the weights, but
give an upper bound of the worst case (which is usually
too pessimistic).
A much more accurate number could be found by simu-
lating the arbiter, e.g. if the settings are: CPU
L2
D
giving 4 requests. But actually the worst case grant re-
quests order is: CPU, L3, VO - resulting in 3 requests
only.
20.5.2
In the following, ceil(x) means the least integral value
greater than or equal to x.
Minimum allocated bandwidth, B
biter is defined as follows:
B
20-6
D
D
D
D
D
x
VO
2
3
4
5
6
weight
= (M
ceil(16 * 2 / (5 / 4)] = 315 SDRAM cycles
VO,sc
VO
=
=
=
=
=
2
VO
= ceil[(1 + 1) / 1] * ceil[(1 + 2) / 2]
is ceil[(3 + 2) / 2] = 3,
ceil
ceil
ceil
ceil
ceil
= L
cycles
=2, VO
is ceil[(3 + 7) / 3] * 3 +1 = 13.
= 13 * 20 + 10 + ceil[13 * 20 / 1220] * 19 +
Bandwidth Analysis
VO,sc
weight
⎛
⎝
⎛
⎝
⎛
⎝
⎛
⎝
⎛
⎝
CPU
----------------------------------------------------- -
VO
------------------------------------------------- -
ICP
--------------------------------------------------- -
VI
----------------------------------------------- -
PCI
--------------------------------------------------- -
- K
weight
weight
d
* 12.5 = 3937.5 ns
k
weight
is 7, then
) * S / [T * E
weight
weight
is 1220 cycles, and R
weight
L5
{AI,AO,VLD}
L3
L4
L6
L2
=1 and L3
weight
weight
+
weight
weight
PRELIMINARY SPECIFICATION
weight
+
weight
+
+
L5
+
L3
L4
L6
L2
weight
weight
weight
weight
x
is 3, L2
for AI, AO or VLD.
weight
weight
+ (16 * R
x
⎞
⎠
x
when a unit is not en-
⎞
⎠
for a unit x, by the ar-
⎞
⎠
×
⎞
⎠
=1, then
⎞
⎠
×
weight
×
×
D
D
D
4
D
x
2
x
3
5
/ C)]
is 2, then the
is 2, VO
weight
{2,3,4,5,6}
weight
=1,
Where:
M
a period P in which the bandwidth is computed. For ex-
ample, if the period is 1 second and SDRAM runs at 80
MHz then M
K
during the same period P.
If P is in seconds it could be expressed as:
K
For example, if P is 1 second then K
ceil(4096 * 1 / .064) * 19 = 1216000 SDRAM cycles.
S is the size of the transaction on the bus.
For PNX1300, S is equal to 64 (bytes).
E
to the arbiter settings.
It means the unit x will get 1 / E
E
Where:
E
E
E
E
E
E
E
E
E
E
E
E
E
k
k
x
x
cycles
VLD
AI
AO
DVDD
SPDO
ICP
2
3
4
CPU
VO
VI
PCI
= ceil(4096 * P / .064) * K
is the ratio of requests available for a unit x according
is derived from the arbiter settings as follows:
is the amount of SDRAM cycles used by the refresh
=
=
=
=
=
=
=
=
=
CPU
----------------------------------------------------- -
VO
------------------------------------------------- -
ICP
--------------------------------------------------- -
=
is the total amount of SDRAM cycles available in
=
2
-------------------------------------------------
VI
----------------------------------------------- -
2
-------------------------------------------------
=
VO
------------------------------------------------- -
=
ICP
--------------------------------------------------- -
PCI
--------------------------------------------------- -
+ + + + +
2
-------------------------------------------------
CPU
----------------------------------------------------- -
+ + + + +
weight
weight
2
-------------------------------------------------
weight
+ + + + +
2
-------------------------------------------------
1
cycles
weight
weight
1
L3
+ + + + +
L4
+ + + + +
1
weight
VI
weight
L2
VO
ICP
PCI
1
weight
1
1
CPU
weight
weight
weight
1
weight
+
+
is 80,000,000.
1
1
+
weight
1
+
+
1
L3
L5
1
weight
weight
2
0
L4
0
+
+
L3
1
L2
weight
1
0
weight
weight
+
L4
L6
weight
0
1
0
weight
weight
L2
1
weight
weight
1
Philips Semiconductors
1
weight
1
1
1
×
×
×
1
×
x
×
×
E
E
1
1
×
E
out of the total requests.
E
×
×
E
2
E
4
×
6
×
3
E
6
E
2
E
E
6
E
3
5
k
6
6
is