PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 32

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
1-6
VO_IO1
VO_IO2
VO_CLK
AI_OSCLK
AI_SCK
AI_SD
AI_WS
Pin Name
BGA
Ball
H20
C15
B15
A16
B16
J18
J19
PRELIMINARY SPECIFICATION
Audio In (always acts as receiver, but can be master or slave for A/D timing)
WEAK5
WEAK5
WEAK5
WEAK5
STRG5
STRG3
STRG5
Type
Pad
Mode
OUT
I/O
I/O
I/O
I/O
I/O
IN
This pin can function as HS output or as STMSG (Start Message) output.
• If set as HS output, it outputs the horizontal sync signal
• In message passing mode, this pin acts as STMSG output.
This pin can function as FS (frame sync) input, FS output or as ENDMSG output.
• If set as FS input, it can be set to respond to positive or negative edge transitions.
• If the Video Out (VO) unit operates in external sync mode and the selected transition
• In message passing mode, this pin acts as ENDMSG output.
The VO unit emits VO_DATA on a positive edge of VO_CLK. VO_CLK can be config-
ured as input (reset default) or output.
• If configured as input: VO_CLK is received from external display clock master cir-
• If configured as output, PNX1300/01/02/11 emits a programmable clock frequency.
If used as output, a board level 27-33 ohm series resistor is recommended to reduce
ringing.
Over-sampling clock. This output can be programmed to emit any frequency up to 40
MHz with a sub-Hertz resolution. It is intended for use as the 256f
pling clock by external A/D subsystem. A board level 27-33 ohm series resistor is rec-
ommended to reduce ringing.
• When the Audio In (AI) unit is programmed as a serial-interface timing slave
• When the AI unit is programmed as the serial-interface timing master, AI_SCK is an
AI_SCK is limited to 22 MHz. The sample rate of valid samples embedded within the
serial stream is variable. If used as output, a board level 27-33 ohm series resistor is
recommended to reduce ringing.
Serial data from external A/D subsystem. Data on this pin is sampled on positive or
negative edges of AI_SCK as determined by the CLOCK_EDGE bit in the AI_SERIAL
register.
• When the AI unit is programmed as the serial-interface timing slave (power-up
• When Audio In is programmed as the serial-interface timing master, AI_WS acts as
AI_WS is the word-select or frame-synchronization signal from/to the external A/D
subsystem.
occurs, the VO unit sends two fields of video data. Note: this works only once after a
reset.
cuitry.
The emitted frequency can be set between approx. 4 and 81 MHz with a sub-Hertz
resolution. The clock generated is frequency accurate and has low jitter properties
due to a combination of an on-chip DDS (Direct Digital Synthesizer) and VCO/PLL.
(power-up default), AI_SCK is an input. AI_SCK receives the serial bit clock from
the external A/D subsystem. This clock is treated as fully asynchronous to the
PNX1300/01/02/11 main clock.
output. AI_SCK drives the serial clock for the external A/D subsystem. The fre-
quency is a programmable integral divisors of the AI_OSCLK frequency.
default), AI_WS acts as an input. AI_WS is sampled on the same edge as selected
for AI_SD.
an output. It is asserted on the opposite edge of the AI_SD sampling edge.
Description
Philips Semiconductors
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or 384f
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over sam-