IPPOSPHYL2 Altera, IPPOSPHYL2 Datasheet - Page 52

• Manufacturer Part Number: IPPOSPHYL2
• Manufacturer: Altera

Specifications of IPPOSPHYL2

• Lead Free Status / RoHS Status: Not Compliant

3–24
Table 3–11. POS-PHY Level 2 Transmit Interface (Part 2 of 2)
Table 3–12. POS-PHY Level 2 Receive Interface (Part 1 of 3)
POS-PHY Level 2 and 3 Compiler User Guide
ptpa
dtpa[x]
tfclk
Notes to
(1) The 8-bit mode is an Altera extension to the POS-PHY Level 2 specification.
(2) Not present in 8-bit mode.
(3) Packet-level mode only.
(4) Byte-level mode only.
rdat[15/7:0]
(1)
rprty
Signal
Signal
(3)
Table
(4)
3–11:
1
PHY to link
PHY to link
Table 3–12
All these signals are compliant with the POS-PHY Level 2 Specification, Issue 5,
December 1998.
Direction
PHY to link
PHY to link
Link to PHY Transmit FIFO buffer write clock. tfclk is used to synchronize data transfer
Direction
describes the POS-PHY level 2 receive interface.
Receive parity signal. rprty signal indicates the parity of the rdat bus. When
Receive packet data bus. The rdat bus carries the packet octets that are read from the
selected receive FIFO buffer. rdat is valid only when renb is simultaneously asserted
and a valid PHY-layer device has been selected via the radr signals. Data must be
received in big-endian order. Given the defined data structure, bits are received in the
following order: 15, 14 … 8, 7, 6 … 1, 0. The PHY-layer device tri-states rdat when
renb is high. rdat is also tri-stated when either the null-PHY address (1Fh) or an
address not matching the PHY-layer device address is presented on the radr signals
when renb is sampled high (has been deasserted during the previous clock cycle).
rprty is supported, the PHY-layer device must support both odd and even parity. The
PHY-layer device tri-states rprty when renb is high. rprty is also tri-stated when
either the null-PHY address (1Fh), or an address not matching the PHY-layer device
address, is presented on the radr signals when renb is sampled high (has been
deasserted during the previous clock cycle).
Polled-PHY transmit packet available signal. ptpa transitions high when
fifo_threshold words is available in the polled transmit FIFO buffer. When
high, ptpa indicates that the transmit FIFO buffer is not full. When ptpa transitions
low, it indicates that the transmit FIFO buffer has reached fifo_threshold
words. PTPA allows to poll the PHY address selected by tadr when tenb is
asserted. ptpa is driven by a PHY-layer device when its address is polled on tadr.
A PHY-layer device tri-states ptpa when either the null-PHY address (0x1F) or an
address not matching available PHY-layer devices is provided on tadr.
Direct transmit packet available. dtpa[x] provides direct status indication for the
corresponding port (referred to by the index “x”). dtpa[x] transitions high when
fifo_threshold words are available in the transmit FIFO buffer. When high,
dtpa[x] indicates that the transmit FIFO buffer is not full. When dtpa[x]
transitions low, it indicates that the transmit FIFO buffer has reached
fifo_threshold words.
transactions from the link-layer device to the PHY-layer device. tfclk can cycle at
any rate from 25 MHz up to 50 MHz.
Preliminary
Description
Description
© November 2009 Altera Corporation
Chapter 3: Functional Description
Interface Signals