M38510/20304BFA E2V, M38510/20304BFA Datasheet - Page 26

• Manufacturer Part Number: M38510/20304BFA
• Manufacturer: E2V

Specifications of M38510/20304BFA

• Lead Free Status / RoHS Status: Supplier Unconfirmed

procedures shall be used for programming.
4.10 Programming procedure for circuit G. The programming characteristics on table IVD and the following
a. Connect the device in the electrical configuration of programming. The waveforms on figure 5d and the
c. Increase V
d. Select the output where a logical high is desired by raising that output voltage to V
e. Enable the device by taking the chip enable(s) to a low level. This is done with a pulse PWE for 10 μs.
f. Verify that the bit has been programmed by first removing the programming voltage from the output and
g. If the device is not to be tested for V
h. Repeat steps 4.10b through 4.10f for each bit to be programmed to a high level. If the procedure is
i. If any bit does not verify as programmed it shall be considered a programming reject.
i. To verify programming, after t
j. If any bit does not verify as programmed it shall be considered a programming reject.
b. Select the desired word by applying high or low levels to the appropriate address inputs. Disable the
to
programming characteristics of table IVD shall apply to these procedures.
device by applying a high level to one or more ‘active low’ chip Enable inputs. NOTE: Address and Enable
inputs must be driven with TTL logic levels during programming and verification.
the source of the current required to program the fuse as well as the I
voltage, it must be capable of supplying 750 mA at 11.0 volts.
the slew rate to I
increase to V
the internal circuits can only supply programming current to one bit at a time. Outputs not being
programmed must be left open or connected to a high impedance source of 20 kΩ minimum (remember
that the outputs of the device are disabled at this time).
The 10 μs duration refers to 5.0 V (±0.25). The time that the circuit (device) is enabled, normal input levels
are used and rise and fall times are not critical.
then reducing V
During verification, the loading of the output must be within specified I
verification of step 4.10f is to be performed at a V
verification, must be at least 2.0 V. The 4.0 V V
operating range.
performed on an automatic programmer, the duty cycle of V
to a maximum of 25%. This is necessary to minimize device junction temperatures. After all selected bits
are programmed; the entire contents of the memory should be verified.
V
CC
CE and
to V
1
CCL
CC
= +4.5 ± 0.2 V, and verify that the programmed output remains in the “1” state.
CE
CCP
from nominal to V
CC
2
, but must not precede it. It is critical that only one output at a time be programmed since
RR
inputs. The programmed output should remain in the “1” state. Again, lower
to 5.0 V (±0.25 V). The device must be Enabled to sense the state of the outputs.
(1.0 to 10.0 V/μs). This voltage change may occur simultaneously with the V
D
(10 μs) delay, lower V
CCP
(10.5 ±0.5 V) with a slew rate limit of I
OH
MIL-M-38510/203E
over the entire operating range subsequent to programming, the
26
CC
CC
verification assures minimum V
level of 4.0 volt (±0.2 V). V
CC
to V
CC
CCH
at the programming voltage must be limited
= +5.5 ± 0.2 V, and apply a logic “0” level
CC
OL
for the device at the programming
and I
RR
(1.0 to 10.0 V/μs). Since V
OH
OH
limits.
, during the 4 V
OH
OP
levels over the entire
(10.5 ±0.5 V). Limit
CC
CC
is