SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 50

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.4.2
54
Signal Name
MD[63:0]
MA[12:0]
BA1
BA0
CS1#
CS0#
RASA#
CASA#
WEA#
DQM7
DQM6
DQM5
DQM4
DQM3
DQM2
DQM1
DQM0
CKEA
SDCLK3
SDCLK2
SDCLK1
SDCLK0
Memory Interface Signals
Table 3-3
Table 3-3
Ball No.
on page
on page
AK14
AH27
AK12
AH12
AB31
AG29
AK21
AC31
AG30
AH23
AA28
32580B
AL12
AL15
AL11
AL22
AJ13
AJ12
AJ21
W29
See
See
V29
41.
41.
Type
I/O
O
O
O
O
O
O
O
O
O
Description
Memory Data Bus. The data bus lines driven to/from
system memory.
Memory Address Bus. The multiplexed row/column
address lines driven to the system memory. Supports
256-Mbit SDRAM.
Bank Address Bits. These bits are used to select the
component bank within the SDRAM.
Chip Selects. These bits are used to select the module
bank within system memory. Each chip select corre-
sponds to a specific module bank. If CS# is high, the
bank(s) do not respond to RAS#, CAS#, and WE# until
the bank is selected again.
Row Address Strobe. RAS#, CAS#, WE# and CKE are
encoded to support the different SDRAM commands.
RASA# is used with CS[1:0]#.
Column Address Strobe. RAS#, CAS#, WE# and CKE
are encoded to support the different SDRAM commands.
CASA# is used with CS[1:0]#.
Write Enable. RAS#, CAS#, WE# and CKE are encoded
to support the different SDRAM commands. WEA# is
used with CS[1:0]#.
Data Mask Control Bits. During memory read cycles,
these outputs control whether SDRAM output buffers are
driven on the MD bus or not. All DQM signals are
asserted during read cycles.
During memory write cycles, these outputs control
whether or not MD data is written into SDRAM.
DQM[7:0] connect directly to the [DQM7:0] pins of each
DIMM connector.
Clock Enable. These signals are used to enter Suspend/
power-down mode. CKEA is used with CS[1:0]#.
If CKE goes low when no read or write cycle is in
progress, the SDRAM enters power-down mode. To
ensure that SDRAM data remains valid, the self-refresh
command is executed. To exit this mode, and return to
normal operation, drive CKE high.
These signals should have an external pull-down resistor
of 33 KΩ.
SDRAM Clocks. SDRAM uses these clocks to sample
all control, address, and data lines. To ensure that the
Suspend mode functions correctly, SDCLK3 and
SDCLK1 should be used with CS1#. SDCLK2 and
SDCLK0 should be used together with CS0#.
AMD Geode™ SC2200 Processor Data Book
Signal Definitions
Mux
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