SC2200UFH-300 AMD (ADVANCED MICRO DEVICES), SC2200UFH-300 Datasheet - Page 53

• Manufacturer Part Number: SC2200UFH-300
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC2200UFH-300

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Definitions
3.4.5
3.4.6
AMD Geode™ SC2200 Processor Data Book
Signal Name
AB1D
AB2C
AB2D
Signal Name
PCICLK
PCICLK0
PCICLK1
AD[31:24]
AD[23:0]
C/BE3#
C/BE2#
C/BE1#
C/BE0#
INTA#
INTB#
INTC#
INTD#
ACCESS.bus Interface Signals (Continued)
PCI Bus Interface Signals
BalL No.
Table 3-3
Ball No.
on page
M29
N30
N29
See
D26
C26
AA2
41.
D6
H4
C9
A7
A4
F3
J2
L1
Type
Type
I/O
I/O
I/O
I/O
I/O
O
O
I
I
Description
ACCESS.bus 1 Serial Data. This is the bidirectional
serial data signal for the interface.
Note:
ACCESS.bus 2 Serial Clock. This is the serial clock for
the interface.
Note:
ACCESS.bus 2 Serial Data. This is the bidirectional
serial data signal for the interface.
Note:
Description
PCI Clock. PCICLK provides timing for all transactions
on the PCI bus. All other PCI signals are sampled on the
rising edge of PCICLK, and all timing parameters are
defined with respect to this edge.
PCI Clock Outputs. PCICLK0 and PCICLK1 provide
clock drives for the system at 33 MHz. These clocks are
asynchronous to PCI signals. There is low skew between
all outputs. One of these clock signals should be con-
nected to the PCICLK input. All PCI clock users in the
system (including PCICLK) should receive the clock with
as low a skew as possible.
Multiplexed Address and Data. A bus transaction con-
sists of an address phase in the cycle in which FRAME#
is asserted followed by one or more data phases. During
the address phase, AD[31:0] contain a physical 32-bit
address. For I/O, this is a byte address. For configuration
and memory, it is a DWORD address. During data
phases, AD[7:0] contain the least significant byte (LSB)
and AD[31:24] contain the most significant byte (MSB).
Multiplexed Command and Byte Enables. During the
address phase of a transaction when FRAME# is active,
C/BE[3:0]# define the bus command. During the data
phase, C/BE[3:0]# are used as byte enables. The byte
enables are valid for the entire data phase and determine
which byte lanes carry meaningful data. C/BE0# applies
to byte 0 (LSB) and C/BE3# applies to byte 3 (MSB).
PCI Interrupts. The SC2200 provides inputs for the
optional “level-sensitive” PCI interrupts (also known in
industry terms as PIRQx#). These interrupts can be
mapped to IRQs of the internal 8259A interrupt control-
lers using PCI Interrupt Steering Registers 1 and 2
(F0 Index 5Ch and 5Dh).
Note:
If AB1D function is selected but not used, tie
AB1D high.
If AB2C function is selected but not used, tie
AB2C high.
If AB2D function is selected but not used, tie
AB2D high.
If selected as INTC# or INTD# function(s) but not
used, tie INTC# and INTD# high.
32580B
GPIO19+IOCHRDY
FPCI_MON (Strap)
LPC_ROM (Strap)
GPIO1+IOCS1#
IDE_DATA7
GPIO12
GPIO13
A[23:0]
D[7:0]
Mux
Mux
D11
D10
D9
D8
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