LE58QL02FJC Zarlink, LE58QL02FJC Datasheet
LE58QL02FJC
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LE58QL02FJC Summary of contents
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... Le58QL061/063 QLSLAC™ Device Data Sheet 080761 QSLAC™ to QLSLAC™ Device Design Conversion Guide 080758 QSLAC™ to QLSLAC™ Guide to New Designs Le58QL02/021/031 ORDERING INFORMATION Device Package (Green) Le58QL02FJC 44-pin PLCC Le58QL021FJC 44-pin PLCC Le58QL021BVC 44-pin TQFP Le58QL031DJC 32-pin PLCC 1 ...
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... Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Channel Enable (EC) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 SLIC Device Control and Data Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Clock Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 E1 Multiplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Debounce Filters Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Real-Time Data Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Active State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Inactive State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Chopper Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 SIGNAL PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2 Zarlink Semiconductor Inc. ...
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... CDh Read Transmit PCM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 E8/E9h Write/Read Ground Key Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 PROGRAMMABLE FILTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 General Description of CSD Coefficients .56 User Test States and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 A-Law and µ-Law Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Controlling the SLIC Device .60 Calculating Coefficients with WinSLAC Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3 Zarlink Semiconductor Inc. ...
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... APPLICATION CIRCUIT .61 LINE CARD PARTS LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 PHYSICAL DIMENSIONS .62 32-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 44-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Revision .65 Revision .65 Revision .65 Revision .65 Revision .65 Revision .65 Revision .65 Revision F2 to Version .65 4 Zarlink Semiconductor Inc. ...
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... Table 1. QLSLAC Device Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 2. 0 dBm0 Voltage Definitions with Unity Gain GX, GR, AX, and .14 Table 3. Channel Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 4. Channel Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 5. Global Chip Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 6. Global Chip Status Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 7. A-Law: Positive Input Values .58 Table 8. µ-Law: Positive Input Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 5 Zarlink Semiconductor Inc. ...
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... This block communicates digitally with the SLIC device circuits. It sends control bits to the SLIC devices to control modes and to operate LEDs and optocouplers. It also accepts supervision information from the SLIC devices and performs some filtering. Chopper Clock per Channel Four I/O Yes Five I/O No Two I Zarlink Semiconductor Inc. Package Part Number 44 PLCC Le58QL02JC 44 PLCC/TQFP Le58QL021JC (or VC) 32 PLCC Le58QL031JC ...
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... CONNECTION DIAGRAMS VOUT VIN VOUT VIN VCCA VREF AGND VIN VOUT VIN VOUT Figure 1. Le58QL02JC 44-Pin PLCC Le58QL02JC 12 44-Pin PLCC Zarlink Semiconductor Inc DCLK 38 DIO 37 TSCA TSCB 36 35 DGND 34 PCLK 33 VCCD 32 DXA 31 DXB RST ...
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... Figure 3. Le58QL031JC 32-Pin PLCC VIN 5 1 VOUT 6 2 VIN 7 2 VCCA 8 Le58QL031JC VREF 9 32-Pin PLCC AGND 10 VIN 11 3 VOUT 12 3 VIN Zarlink Semiconductor Inc DCLK 37 DIO 36 TSCA 35 DGND 34 PCLK 33 VCCD 32 DXA RST 29 INT DCLK 29 DIO 28 TSCA 27 DGND 26 PCLK 25 VCCD 24 DXA 23 FS ...
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... Figure 4. Le58QL021VC 44-Pin PLCC VOUT 1 1 VIN 2 1 VOUT 3 2 VIN 4 2 VCCA 5 Le58QL021VC VREF 6 44-Pin TQFP AGND 7 VIN 8 3 VOUT 9 3 VIN 10 4 VOUT Zarlink Semiconductor Inc DCLK 31 DIO 30 TSCA DGND 29 PCLK 28 27 VCCD DXA RST 24 INT 23 ...
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... Data. Control data is serially written into and read out of the QLSLAC device via the DIO pin, with the most significant bit first. The Data Clock determines the data rate. DIO is high impedance except when data is being transmitted from the QLSLAC device. 10 Zarlink Semiconductor Inc. Operating the , and C5 I/Os are eliminated, enabling dual ...
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... VIN 3 is the output from channel 1, VOUT 1 is the output from channel 3, and VOUT 3 Electrical Characteristics, on page 11 Zarlink Semiconductor Inc. is the input for channel 1, VIN the input for channel the output for 2 is the output for channel 4. The 4 13 ...
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... C < T < +85° 95% –0 4.0 V ±0.4 V –0 4.0 V –0 0.4 V) CCA ±50 mV –0 VCCD + 2.37 V, whichever is smaller ± 100 mA 0.5 A –40° C < T < +85° 85% +3.3 V ± ± CCD +3.3 V ± ±10 mV 0.1 µF ± 20% DGND to +5. Zarlink Semiconductor Inc. ...
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... C Digital Output capacitance O Power supply rejection ratio (1.02 kHz, 100 mV PSRR path dB) = 400 µ state AGND OUT , either RMS 13 Zarlink Semiconductor Inc. Min Typ Max Unit 0.8 V 2.0 –7 +7 µA –120 +180 0.16 0.25 0.34 V 0.4 0.8 V 0.4 0.4 – ...
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... Hz 0 dBm0 300 to 3400 Hz 0 dBm0 SLIC imped. < 300 Ω 1014 Hz, Average 1014 Hz, Average 2..N) are closely spaced Zarlink Semiconductor Inc. , then the output offset will be multiplied AISN Receive Unit 0.5024 0.4987 Vrms 0.5024 Min Typ Max Unit – ...
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... N ⎜ ⎟ log ---- - ⎝ ⎠ Figure 6. The reference frequency is 1014 Hz and the signal level is Acceptable Region Frequency (Hz) Acceptable Region Frequency (Hz) 15 Zarlink Semiconductor Inc. ) ⎛ ⎞ • ⎜ ⎟ log --------- - ⎝ ⎠ – – 10 dBm0. 0.75 0 0.80 ...
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... For either transmission path, the group delay distortion is within the limits shown in delay is taken as the reference. The signal level should be 0 dBm0. 420 Delay (µS) 150 90 Figure 7. Group Delay Distortion Acceptable Region 0 Frequency (Hz) 16 Zarlink Semiconductor Inc. Figure 7. The minimum value of the group ...
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... Acceptable Region 0 -55 -50 -40 µ -law Gain Linearity with Tone Input (Both Paths) 1.4 Acceptable Region 0 -55 -50 -37 17 Zarlink Semiconductor Inc. µ Figure 8 (A-law) and Figure 9 ( -law) for either Input Level - (dBm0) Input Level +3 -10 0 ...
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... The signal to total distortion ratio will exceed the limits shown in signal of frequency 1014 Hz. Figure 10. Total Distortion with Tone Input (Both Paths -45 -40 Figure 10 for either path when the input signal is a sine wave Acceptable Region -30 Input Level (dBm0) 18 Zarlink Semiconductor Inc. A A-Law µ-Law A 35.5dB 35.5dB B 35.5dB 35.5dB C 30dB 31dB D ...
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... A ≤ 0 dBm0 –25 dBm0 < A ≤ 0 dBm0 –25 dBm0 < A ≤ 0 dBm0 0 -10 -20 -30 -40 -50 3.4 4.0 4.6 Frequency (kHz) π 4000 f – ⎛ ---------------------------- - Attenuation (db – sin ⎝ 19 Zarlink Semiconductor Inc. Level below see Figure - ⎞ ⎠ 1200 ...
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... Level = 14 14 sin – – ⎝ 1200 Figure 12. Spurious Out-of-Band Signals 0 -10 -20 -30 -40 -50 3.4 4.0 4.6 Frequency (kHz) 20 Zarlink Semiconductor Inc. Level –32 dBm0 –46 dBm0 –36 dBm0 12. The amplitude of the spurious out-of-band ) ⎞ dBm0 ⎠ -28 dBm0 -32 dBm0 ...
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... The conditions for this figure are: 1.2 dB < GX ≤ –12 dB ≤ GR < –1 Digital voice output connected to digital voice input. 4. Measurement analog-to-analog. Figure 13. Analog-to-Analog Overload Compression Fundamental Output Power (dBm0 Acceptable Fundamental Input Power (dBm0) 21 Zarlink Semiconductor Inc. Region ...
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... DRS t 36 PCM data input hold time DRH Parameter Min 122 2500 2500 3 50 Parameter Min. 122 Zarlink Semiconductor Inc. Typ Max Unit Note –10 DCY t –20 DCH 8t DCY 1 ns 2500 t –10 DCY t –20 DCH 8t DCY µs Typ Max Unit Note ...
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... Phase jumps will be present when the master clock frequency is a multiple of 1.544 MHz. 26.) Parameter Master clock jitter Rise time of clock Fall time of clock MCLK HIGH pulse width MCLK LOW pulse width Parameter CHP = 0 CHP = 1 , where N is the value stored in the time/clock-slot register. PCY 23 Zarlink Semiconductor Inc. Min Typ Max Unit Min Typ Max ...
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... SWITCHING WAVEFORMS Figure 14. Input and Output Waveforms for AC Tests 2.4 V 0.45 V Figure 15. Microprocessor Interface (Input Mode DCLK Data D I/O Valid Outputs 2.0 V TEST POINTS 0 Data Data Valid Valid Data Valid 24 Zarlink Semiconductor Inc. 2 Data Valid ...
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... V Three-State Data OH D I/O Valid V OL Figure 17. PCM Highway Timing for (Transmit on Negative PCLK Edge PCLK TSCA/ TSCB DXA/DXB DRA/DRB Data Data Valid Valid Time Slot Zero Clock Slot Zero First Bit First Second Bit Bit Zarlink Semiconductor Inc Three-State ...
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... Figure 18. PCM Highway Timing for (Transmit on Positive PCLK Edge PCLK TSCA/ TSCB DXA/DXB DRA/DRB Time Slot Zero Clock Slot Zero First Bit First Second Bit Bit V IL Figure 19. Master Clock Timing Zarlink Semiconductor Inc ...
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... The PCM clock (PCLK) is used for PCM timing and is an integer multiple of the frame sync frequency. The internal master clock can be optionally derived from the PCLK source by setting the CMODE bit (bit 4, Command 46/47h) to one. In this mode, the MCLK/E1 pin is free to be used signal output. Clock mode options and E1 output functions are shown in Figure 20. 27 Zarlink Semiconductor Inc. ...
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... CMODE ÷ N DSP Engine CSEL E1 Pulses E1P Notes: 1. CMODE = Command 46/47h 2. CSEL = Command 46/47h 3. EE1 = Command C8/C9h 4. E1P = Command C8/C9h 28 Zarlink Semiconductor Inc. . MCLK/ EE1 Bit 4 Bits 0–3 Bit 7 Bit 6 µ µ s before allowing any change to the CD1 s (1/32 kHz) ...
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... Command GK Enable E8/E9h) (Channel 1 Shown) { Same for Channels CDB CDA 4 ATI (Command 70/71h) MCDB MCDA MCDB MCDA Zarlink Semiconductor Inc CD2 CD1 0 MUX Debounce (time set via Command C8/C9h) Real Time Data Register (Command 4D/4Fh) CDB CDA CDB CDA CDB CDA ...
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... Contains CD1 Pin CD1 Pin State State Valid GK Ignored Ignored Status Hold Last State Tracks Hold Last State Hold Last State DET State Figure 23a for this filter’s operation. 30 Zarlink Semiconductor Inc. Contains Valid LD Status Tracks DET State ...
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... If any of the inputs to the unmasked bits in the Real Time Data register are different from Figure 23. MPI Real-Time Data Register DSH0 – DSH3 Debounce Period (0 – Loop Detect Debounce Filter MUX UP/DN Q Six-State RST Up/Down Clock Divider Counter (1 – clock output) b. Ground-Key Filter 31 Zarlink Semiconductor Inc CDA Debounce Counter EN/HOLD * Q CK RST CDB ...
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... The supervision debounce time is set to 8 ms. 15. The chopper clock frequency is set to 256 kHz but the chopper clock is turned off. 16. The E1 Multiplex state is turned off (E1 is Hi-Z) and the polarity is set for high going pulses. 17. No signalling on the PCM highway. 32 Zarlink Semiconductor Inc. ...
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... Inter- Inter polator polator * Lower Receive Gain (LRG) * programmable blocks (See GIN in Electrical Characteristics, on page IN OUT 33 Zarlink Semiconductor Inc. Cutoff Transmit Path (CTP) LPF & Com- X TSA HPF pressor * TSA Loopback (TLB) Cutoff Receive Path (CRP) Ex- Digital R LPF TSA pander ...
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... RAM, while analog amplifier which can be programmed for 6.02 dB loss. The Z, R, and GR filters can also be operated from an alternate set of default coefficients stored in ROM (Command 60/61h). for the value). Gain block analog gain 6.02 dB (unity gain or gain 34 Zarlink Semiconductor Inc. ...
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... SLIC device echo gain into a short circuit, and Z 44 ⎛ 4 ⎜ ∑ • h 0.0625 GIN AISN = ⎜ AISN ⎝ value of AISN = 00000 specifies a gain of 0 (or cutoff), and 2) a value AISN 35 Zarlink Semiconductor Inc. ) given by: IN • 440 AISN ⎞ ⎟ i • – ⎟ i ⎠ is the SL ...
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... The previous frame sync pulse (FS) was not two PCLK cycles long. The frame sync pulse is sampled on the falling edge of PCLK. As shown in Figure 25, if the above criteria is met, and high for two consecutive falling edges of PCLK then low for the third falling edge considered a robbed-bit frame. Otherwise normal frame. 36 Zarlink Semiconductor Inc. ...
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... Figure 25. Robbed-Bit Frame PCLK FS Normal Frame (Not Robbed-Bit) PCLK FS Robbed-Bit Frame page 61. This SLIC device has a transmit gain of 0.5 (GTX) and a current 37 Zarlink Semiconductor Inc. ...
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... FDL Full Digital Loopback TON 1 kHz Tone On GK Ground-Key Filter CSTAT Select Active or Inactive (Standby) state Commands are provided to read values from the following channel monitors: Description 38 Zarlink Semiconductor Inc. MPI 40/41h 42/43h 80/81h 82/83h 86/87h 96/97h 88/89h 8A/8Bh 98/99h 9A/9Bh ...
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... An MPI cycle is defined by transitions of CS and DCLK. If the CS lines are held in the High state between accesses, the DCLK may run continuously with no change to the internal control data. Using this method, the same DCLK can be run to a number of Description Description Description 39 Zarlink Semiconductor Inc. MPI 53h 53h CDh MPI ...
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... Write/Read R Filter Coefficients Write/Read B2 Filter Coefficients (IIR) Write/Read Z Filter Coefficients (FIR only) Write/Read Z Filter Coefficients (IIR only) Write/Read Debounce Time Register Read Transmit PCM Data Write/Read Ground Key Filter Sampling Interval m , refer to the General Description of CSD Coefficients section Zarlink Semiconductor Inc. page 56. ...
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... Activate Channel (Operational State) Command This command places the device in the Active state and sets CSTAT = 1. No valid PCM data is transmitted until after the third FS pulse is received following the execution of the Activate command page 32 of the section Operating the QLSLAC Device Zarlink Semiconductor Inc ...
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... TAB XE RCS2 RCS1 Transmit data on highway selected by TPCM (See Command 40/41h on Transmit data on both highways A and B Transmit changes on negative edge of PCLK Transmit changes on positive edge of PCLK Receive Clock Slot number Transmit Clock Slot number 42 Zarlink Semiconductor Inc R/W TTS3 TTS2 TTS1 ...
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... MCLK used as master clock multiplexing allowed PCLK used as master clock; E1 multiplexing allowed if enabled in commands C8/C9h. 1.536 MHz 1.544 MHz 2.048 MHz Reserved Two times frequency specified above (2 x 1.536 MHz, Four times frequency specified above (4 x 1.536 MHz, Reserved 8.192 MHz is the default 43 Zarlink Semiconductor Inc ...
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... Debounced data bit 1 on channel 2 Data bit 2 or multiplexed data bit 1 on channel 2 Debounced data bit 1 on channel 3 Data bit 2 or multiplexed data bit 1 on channel 3 Debounced data bit 1 on channel 4 Data bit 2 or multiplexed data bit 1 on channel 4 44 Zarlink Semiconductor Inc ...
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... See below (Default value = • • • 16 AISN4 8 AISN3 4 AISN2 + + RSVD RSVD CD1B RSVD CSTAT CFAIL IOD5 45 Zarlink Semiconductor Inc R/W AISN3 AISN2 AISN1 AISN0 • AISN1 AISN0 + + – R CD2 CD1 page 45). The ...
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... Default GR filter enabled Programmed GR filter enabled Default GX filter enabled Programmed GX filter enabled Default X filter enabled Programmed X filter enabled Default R filter enabled Programmed R filter enabled Default Z filter enabled Programmed Z filter enabled Default B filter enabled Programmed B filter enabled 46 Zarlink Semiconductor Inc R/W EX ...
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... Transmit Highpass filter disabled 6 dB loss not inserted 6 dB loss inserted Transmit Interrupt not Armed Transmit Interrupt Armed TSA loopback disabled TSA loopback enabled Full digital loopback disabled Full digital loopback enabled 1 kHz receive tone off 1 kHz receive tone on 47 Zarlink Semiconductor Inc ...
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... C10 1.995 (6 dB)). C40 m40 C20 m20 m10 – m20 – m30 { • [ • 1 C20 2 1 C30 0.35547 (–8.984 dB)). GR 48 Zarlink Semiconductor Inc RCN3 RCN2 RCN1 RCN0 R/W C30 m30 C10 m10 m20 m30 – – • [ • ( C20 C30 2 ...
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... C3i C4i 2 m16 m26 – – • { • C26 2 page 48. is the actual IIR filter gain value defined by the programmed coefficients, but it also in- 5 gain and normalization, is actually Zarlink Semiconductor Inc R/W C30 m30 C10 m10 C31 m31 C11 m11 C32 ...
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... B C1i 2 C2i – m111 – m211 • { • = C111 C211 2 11 coefficients page 48. 50 Zarlink Semiconductor Inc R/W C22 m22 C33 m33 C13 m13 C24 m24 C35 m35 C15 m15 C26 m26 C37 m37 C17 m17 C28 m28 C39 m39 ...
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... Sample rate = 16 kHz m1i m2i – – • { • C1i C2i ( page 48. 51 Zarlink Semiconductor Inc R/W C30 m30 C10 m10 C31 m31 C11 m11 C32 m32 C12 m12 C33 m33 C13 m13 C34 m34 C14 m14 C35 m35 C15 m15 – ...
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... FIR m1i m2i – – • { • C1i C2i ( 0.9902) FIR 6 page 48. 52 Zarlink Semiconductor Inc R/W C36 m36 C16 m16 C30 m30 C10 m10 C31 m31 C11 m11 C32 m32 C12 m12 C33 m33 C13 m13 C34 m34 C14 m14 ...
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... C2i 2 1 C3i – m16 – m26 • { • C26 2 + page 48. 53 Zarlink Semiconductor Inc R/W C311 m311 C111 m111 50 R/W C30 m30 C10 m10 C31 m31 C11 m11 C32 m32 C12 m12 C33 ...
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... Z 6 gain. The theoretical effective IIR gain, without the EE1 E1P DSH3 DSH2 E1 multiplexing turned off E1 multiplexing turned high-going pulse low-going pulse 54 Zarlink Semiconductor Inc R/W C35 m35 C15 m15 C16 m16 C37 m37 ...
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... Chopper output (CHCLK) turned off Chopper output (CHCLK) turned XDAT6 XDAT5 XDAT4 RSVD RSVD RSVD µ -law transmit data in Companded mode RSVD RSVD RSVD RSVD Filter sampling period Zarlink Semiconductor Inc XDAT3 XDAT2 XDAT1 XDAT0 RSVD RSVD RSVD RSVD R/W GK3 GK2 GK1 GK0 ...
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... the maximum and minimum values are ±3, i Equation 5 m4 – – • • • – m3 – m4 • ( • Zarlink Semiconductor Inc defined in the following i bits to the right of the decimal 1 bits to the right of the 3 is also 0, the result is another binary – • • • • Equation 6 Equation 7 ...
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... A-law and , consists of N CSD coefficients, each being made bits and formatted coefficient. The most significant binary 1 is represented The next most i Equation 8 page 40 for complete details on programming the coefficients. 57 Zarlink Semiconductor Inc coefficient. 3 µ -law PCM encoding ...
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... Zarlink Semiconductor Inc Character Signal pre Quantized Decoder Inversion of Value (at Output Even Bits Decoder Value No. Output) y Bit No 4032 128 See Note 2112 113 See Note 2 1056 See Note 2 528 ...
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... Zarlink Semiconductor Inc Character Signal pre Quantized Decoder Inversion of Value (at Output Even Bits Decoder Value No. Output) y Bit No 8031 127 See Note 4191 112 See Note 2079 96 See Note 2 1023 See Note 495 64 See Note 2 ...
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... The output from the WinSLAC program includes the coefficients of the GR, GX and B filters as well as transmission performance plots of two-wire return loss, receive and transmit path frequency responses, and four-wire return loss. The software supports the use of the Legerity SLIC devices or allows entry of a SPICE netlist describing the behavior of any type of SLIC device circuit. 60 Zarlink Semiconductor Inc. ...
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... SLIC 2 5 SLIC SLIC 4 Type Value 0.1 µF 0.1 µF 0.1 µF 0.1 µF 57.6 kΩ 0.15 µF 178 kΩ 50 Ω See Note 50 Ω 61 Zarlink Semiconductor Inc. +3 BPD VCCD VCCA U2 Le58QL021 C BPA QLSLAC PCM/MPI AGND VIN1 MLCK/E1 MCLK/E1 VOUT1 PCLK PCLK ...
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... Exact shape of this feature is optional. 0.550 0.553 5 Details of pin 1 identifier are optional but must be located -- 10 deg within the zone indicated. 6 Sum of DAM bar protrusions to be 0.007 max per lead. 7 Controlling dimension : Inch. 8 Reference document : JEDEC MS-016 32-Pin PLCC 62 Zarlink Semiconductor Inc. ...
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... Lead tweeze shall be within 0.0045 inch on each side as measured from a vertical flat plane. Tweeze is measured per AMD 06-500. 9 Lead pocket may be rectangular (as shown) or oval. If corner If corner lead pockets are connected then 5 mils minimum corner lead spacing is required. 44-Pin PLCC 63 Zarlink Semiconductor Inc. Dwg rev. AN; 8/00 ...
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... The top of package is smaller than the bottom of the package by 0.15mm. 12. This outline conforms to Jedec publication 95 registration MS-026 13. The 160 lead is a compliant depopulation of the 176 lead MS-026 variation BGA. 44-Pin TQFP 64 Zarlink Semiconductor Inc. ...
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... Modified GAISN specification in Electrical Characteristics, on page Revision • Enhanced format of package drawings in • Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007. Revision F2 to Version 9 • Modified the content in Package Assembly, on page 12 and R from "Application Circuit" and "Line card Parts List" ...
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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...